Programmable Paging Tone Decoder
CMX823
This bit indicates the status of the tone decoder. A "1" indicates a tone has been
detected (TONE DECODE) and a "0" indicates the loss of the tone (NOTONE) or
the identification of a valid tone which is in the pre-programmed list of the selected
RAM but not in the tone group programmed to be detected, when in NOTONE
state.
TONE DECODE
(Bit 2)
From NOTONE state, TONE DECODE set to "1" means that a tone has been
decoded and its characteristics are as defined by the bandwidth (see CONTROL
Register $30, Bits 5, 4, 3 and 2), the centre frequency and the tone group (see
TONE PARAMETERS Register $34, Bit 15 to Bit 0). An interrupt will be generated.
From NOTONE state, the identification of a valid tone which is not in the pre-
programmed list of the selected RAM (up to 32 tones) will cause the decoder to
move to the TONE DECODE state with the UNLISTED TONE (Bit 1) set to "1",
indicating a valid but unrecognised tone. No interrupt is generated.
From NOTONE state, the identification of a valid tone which is in the pre-
programmed list of the selected RAM but not in the tone group programmed to be
detected, will not cause the decoder to move to the TONE DECODE state and the
UNLISTED TONE (Bit 1) will remain at "0". No interrupt is generated.
From TONE DECODE state, if the decoder detects another tone, either listed or
unlisted, either in the same or in a different tone group, the TONE DECODE bit will
remain at "1". An interrupt will be generated.
Loss of tone will cause the NOTONE timer to be started. If loss of tone continues
for the duration of the time-out period, then the decoder will move to the NOTONE
state and the identification of pre-programmed tones will start again. The time-out
period is not user adjustable. After the CMX823 has deresponded into the
NOTONE state, the internal decoded data history should be cleared by resetting
the GENERAL Register $33 bits 6 and 7 to “0” for a short period (> 10µs). These
bits should then be returned to their previous values. This will ensure that the
decoding of a new tone is not influenced by assessments made on the previous
tone. See Figure 3.
This bit, if set to "1", indicates that an UNLISTED tone has been decoded. This bit
is reset to "0" if a listed tone (of any kind) is decoded.
UNLISTED TONE
(Bit 1)
This bit indicates the RAM that was selected when a match is found for the
decoded tone. A "1" indicates RAM 2, a "0" indicates RAM 1. This bit is undefined if
there is no decoded tone or if the tone is unlisted. No interrupt is generated.
RAM 1 or RAM 2
(Bit 0)
If the DECODE STATUS CHANGE (Bit 3) of the STATUS Register is "1" or the RAM FULL (Bit 4) of the
STATUS Register changes from "0" to "1" or the TONE CHANGE (Bit 5) of the STATUS Register is "1"
then an interrupt will be generated and the IRQN output will be pulled low.
Reading the STATUS Register clears the interrupt (IRQN output goes high) and also clears Bit 3 and Bit
5 of the STATUS Register, if set. A CLEAR RAM command clears Bit 4 of the STATUS Register, if set.
Bits 2, 1 and 0 are set and reset by the action of the tone decoder algorithm, shown in Figure 3. These
are updated every 4.3ms in FAST mode or every 8.6ms in SLOW mode, depending on the setting of the
FAST/SLOW bit of the CONTROL register, after the IRQN pin is pulled low.
In Zero-Power mode, STATUS Register Bits 7 to 0 are preset to “000x0000” respectively.
ã 2003 CML Microsystems Plc
14
D/823/3
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