CMX7163 QAM Modem
CMX7163
7
Detailed Descriptions
7.1 Xtal Frequency
The CMX7163 is designed to work with a Xtal, or an external frequency oscillator within the ranges
specified in section 9.1.3 Operating Characteristics. Program Block 1 (see User Manual) must be loaded
with the correct values to ensure that the device will work to specification with the user selected clock
frequency. A table of configuration values can be found in Table 8 supporting baud rates up to 20k
symbols per second when the Xtal frequency is 9.6MHz or the external oscillator frequency is 9.6 or 19.2
MHz. Rates other than those tabulated (within this range) are possible, see section 10.2.3 Program Block
1 – Clock Control. Further information can be provided on request. The modem can operate with a clock
or Xtal input frequency tolerance of 50ppm. The receive performance will be compromised as the system
tracks, so a maximum tolerance of 20ppm is recommended.
7.2 Host Interface
A serial data interface (C-BUS) is used for command, status and data transfers between the CMX7163
and the host µC; this interface is compatible with Microwire™, SPI™ and other similar interfaces. Interrupt
signals notify the host µC when a change in status has occurred; the µC should read the IRQ Status
register across the C-BUS and respond accordingly. Interrupts only occur if the appropriate mask bit has
been set, see Interrupt Operation.
7.2.1 C-BUS Operation
This block provides for the transfer of data and control or status information between the CMX7163
internal registers and the host µC over the C-BUS serial bus. Single register transactions consist of a
single register address byte sent from the µC, which may be followed by a data word sent from the µC to
be written into one of the CMX7163’s write-only registers, or a data word read out from one of the
CMX7163’s read-only registers. Streaming C-BUS transactions consist of a single register address byte
followed by many data bytes being written to or read from the CMX7163. All C-BUS data words are a
multiple of 8 bits wide, the width depending on the source or destination register. Note that certain C-BUS
transactions require only an address byte to be sent from the µC, no data transfer being required. The
operation of the C-BUS is illustrated in Figure 8.
Data sent from the µC on the CDATA (command data) line is clocked into the CMX7163 on the rising edge
of the SCLK input. Data sent from the CMX7163 to the µC on the RDATA (reply data) line is valid when
SCLK is high. The CSN line must be held low during a data transfer and kept high between transfers. The
C-BUS interface is compatible with most common µC serial interfaces and may also be easily
implemented with general purpose µC I/O pins controlled by a simple software routine. Section 9.2 C-BUS
Timing gives detailed C-BUS timing requirements.
Note that, due to internal timing constraints, there may be a delay of up to 60µs between the end of a C-
BUS write operation and the device reading the data from its internal register.
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