欢迎访问ic37.com |
会员登录 免费注册
发布采购

CMX7163Q1 参数 Datasheet PDF下载

CMX7163Q1图片预览
型号: CMX7163Q1
PDF下载: 下载PDF文件 查看货源
内容描述: [Modem, VQFN-64]
分类和应用: 电信电信集成电路
文件页数/大小: 81 页 / 4386 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
 浏览型号CMX7163Q1的Datasheet PDF文件第12页浏览型号CMX7163Q1的Datasheet PDF文件第13页浏览型号CMX7163Q1的Datasheet PDF文件第14页浏览型号CMX7163Q1的Datasheet PDF文件第15页浏览型号CMX7163Q1的Datasheet PDF文件第17页浏览型号CMX7163Q1的Datasheet PDF文件第18页浏览型号CMX7163Q1的Datasheet PDF文件第19页浏览型号CMX7163Q1的Datasheet PDF文件第20页  
CMX7163 QAM Modem  
CMX7163  
5.3 I/Q Output Reconstruction Filter  
The CMX7163 I/Q Outputs provide internal reconstruction filtering with four selectable bandwidths (-3dB  
point shown in section 10.1.22). The bandwidth of the internal reconstruction filter may be selected using  
the I/Q Output Configuration - $B3 write or Signal Control - $61 write registers.  
To complete the I/Q output reconstruction filter one of the following external RC networks should be used  
for each of the differential outputs. The external RC network should have a bandwidth that matches the  
bandwidth of the selected internal reconstruction filter.  
Bandwidth (kHz) R3-R6 (kOhms)  
C9-C10 (pF)  
100  
50  
25  
22  
20  
22  
22  
33  
75  
150  
270  
12.5  
Figure 6 Recommended External Components I/Q Output Reconstruction Filter  
When transmitting an I/Q signal, each I/Q Output will produce a signal with bandwidth half the channel  
bandwidth. A reconstruction filter with a 3dB point close to half the channel bandwidth will therefore have  
significant roll off within the channel bandwidth which is undesirable. An appropriate choice for channels  
occupying up to a 25kHz bandwidth (channel bandwidth/2 = 12.5kHz) would be a reconstruction filter of  
25kHz bandwidth.  
5.4 I/Q Input Antialias Filter  
The device has a programmable antialias filter in the I/Q input path, which is controlled using the I/Q Input  
Configuration - $B0 write or Signal Control - $61 write registers. This should be sufficient for most  
applications, however if additional filtering is required it can be done at the input to the device.  
The input impedance of the I/Q Input pins varies with the input gain setting, see section 9.1.3 Operating  
Characteristics.  
5.5 GPIO Pins  
All GPIO pins are configured as inputs with an internal bus-hold circuit, after the Function Image™ has  
been loaded. This avoids the need for users to add external termination (pullup/pulldown) resistors onto  
these inputs. The bus-hold is equivalent to a 75kΩ resistor either pulling up to logic 1 or pulling down to  
logic 0. As the input is pulled to the opposite logic state by the user, the bus-hold resistor will change, so  
that it also pulls to the new logic state. The internal bus-hold can be disabled or re-enabled using  
programming register P1.20 in Program Block 1 Clock Control.  
If the device is reset (either by asserting RESETN pin 7, issuing a C-BUS General RESET or by triggering  
an internal power on reset) all GPIO pins will be immediately configured as inputs. Any GPIO pins not  
being pulled either up or down by an external load will be left in a floating state until the Function ImageTM  
is loaded. To avoid GPIO floating input states that may somewhat elevate supply current between a  
RESET and Function ImageTM load, it will be necessary to connect pull up or pull down resistors of 220k  
to these pins.  
2014 CML Microsystems Plc  
Page 16  
D/7163_FI-4.x/12