CMX7163 QAM Modem
CMX7163
6
General Description
6.1 CMX7163 Features
The CMX7163 is intended for use in half-duplex modems. Transmission takes the form of a data burst
consisting of preamble, frame sync and data payload, followed by a tail sequence. Reception may utilise
1
the preamble to assist with signal acquisition , but is then followed by frame sync detection and data
decoding.
A flexible power control facility allows the device to be placed in its optimum powersave mode when not
actively processing signals.
The device includes a Xtal clock generator, with phase locked loop and buffered output, to provide a
System Clock output, if required, for other devices.
Block diagrams of the device are shown in section 2, Block Diagrams.
Tx Functions:
Automatic preamble and frame sync insertion simplifies host control
I/Q analogue outputs
Pulse shape filtering
RAMDAC capability for PA ramping control
Tx trigger feature allowing precise control of burst start time
Tx burst sequence for automatic RAMDAC ramp and Tx hardware switching
Carrier sense for “listen before talk” operation
Raw and formatted (channel coded) data modes
Flexible Tx coded data block size, up to 416 bytes
Rx Functions:
Automatic frame sync detection simplifies host control
I/Q analogue inputs
Rx channel filtering and pulse shape filtering
Channel estimation and equalisation
Tracking of symbol timing and input I/Q dc offsets
AGC using SPI Thru-Port
Raw and formatted (channel coded) data modes
Flexible Rx coded data block size, up to 416 bytes
Auxiliary Functions:
Two programmable system clock outputs
Four auxiliary ADCs with six selectable input paths
SPI Thru-Port for interfacing to synthesisers, Cartesian loop IC (CMX998) and other serially
controllable devices
In-build calibration routine to support CMX998 Cartesian Loop transmitter IC
Four auxiliary DACs, one with built-in programmable RAMDAC
Interface:
Optimised C-BUS (4-wire, high speed synchronous serial command/data bus) interface to host for
control and data transfer, including streaming C-BUS for efficient data transfer
Open drain IRQ to host
Four GPIO pins
Tx trigger input (Provided by GPIOA)
Serial memory or C-BUS (host) boot mode
1
The frame sync detection algorithm of the CMX7163 is capable of detecting a frame sync without having
bit synchronisation, so preamble is not required for obtaining bit sync. Some preamble is still needed to
ensure that the beginning of the frame sync is transmitted and received without distortion. Preamble may
also be used to provide a known signal on which to acquire I/Q dc offset corrections.
2014 CML Microsystems Plc
Page 17
D/7163_FI-4.x/12
CMLMICRO [ CML MICROCIRCUITS ]
