Digital PMR Radio Processor
CMX7131/CMX7141
The number of data bytes following an address byte is dependent on the value of the address byte. The
most significant bit of the address or data are sent first. For detailed timings see section 7.2. Note that,
due to internal timing constraints, there may be a delay of up to 250µs between the end of a C-BUS write
operation and the device reading the data from its internal register.
C-BUS Write:
See Note 1
See Note 2
CSN
SCLK
CDATA
7
MSB
6
5
4
3
2
1
0
LSB
7
MSB
6
…
0
LSB
7
MSB
…
0
LSB
Address/Command byte
Upper 8 bits
Lower 8 bits
RDATA
High Z state
C-BUS Read:
See Note 2
CSN
SCLK
CDATA
7
MSB
6
5
4
3
2
1
0
LSB
Address byte
Upper 8 bits
Lower 8 bits
RDATA
7
MSB
6
…
0
LSB
7
MSB
…
0
LSB
High Z state
Data value unimportant
Repeated cycles
Either logic level valid (and may change)
Either logic level valid (but must not change from low to high)
Figure 15 C-BUS Transactions
Notes:
1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset).
2. For single byte data transfers only the first 8 bits of the data are transferred.
3. The CDATA and RDATA lines are never active at the same time. The Address byte determines
the data direction for each C-BUS transfer.
4. The SCLK input can be high or low at the start and end of each C-BUS transaction.
5. The gaps shown between each byte on the CDATA and RDATA lines in the above diagram are
optional, the host may insert gaps or concatenate the data as required.
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