Digital PMR Radio Processor
CMX7131/CMX7141
6
Detailed Descriptions
6.1 Xtal Frequency
The CMX7131/CMX7141 is designed to work with an external frequency source of 19.2MHz. If this default
configuration is not used then Program Register Block 3 must be loaded with the correct values to ensure
that the device will work to specification with the user selected clock frequency. A table of common values
can be found in Table 9. Note the maximum Xtal frequency is 12.288MHz although an external clock
source of up to 24MHz can be used.
The register values in Table 1 are shown in hex, the default settings are shown in bold, and the settings
which do not give an exact setting (but are within acceptable limits) are in italics. The new P3.2-3 settings
take effect following the write to P3.3. (The settings in P3.4-7 are implemented on a change to Rx or Tx
mode.)
Table 9 Xtal/Clock Frequency Settings for Program Block 3
Program Register
External Frequency Source (MHz)
3.579
6.144
$018
9.216
$018
12.0
12.8
16.368
16.8
19.2
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
GP Timer
$017
$019
$019
$018
$019
$018
VCO output and
AUX clk divide
$085
$043
$398
$140
$008
$088
$040
$200
$140
$008
$08C
$060
$200
$140
$008
$10F
$07D
$200
$140
$008
$110
$0C8
$300
$140
$008
$095
$155
$400
$140
$008
$115
$15E
$400
$140
$008
$099
$0C8
$200
$140
$008
Ref clk divide
PLL clk divide
VCO output and
AUX clk divide
Internal ADC /
DAC clk divide
6.2 Host Interface
A serial data interface (C-BUS) is used for command, status and data transfers between the
CMX7131/CMX7141 and the host µC; this interface is compatible with microwire and SPI. Interrupt signals
notify the host µC when a change in status has occurred and the µC should read the status register across
the C-BUS and respond accordingly. Interrupts only occur if the appropriate mask bit has been set. See
section 6.5.2.
The CMX7131/CMX7141 will monitor the state of the C-BUS registers that the host has written to every
250µs (the C-BUS latency period) hence it is not advisable for the host to make successive writes to the
same C-BUS register within this period.
6.2.1 C-BUS Operation
This block provides for the transfer of data and control or status information between the
CMX7131/CMX7141’s internal registers and the host µC over the C-BUS serial interface. Each transaction
consists of a single address byte sent from the µC which may be followed by one or more data byte(s) sent
from the µC to be written into one of the CMX7131/CMX7141’s Write Only Registers, or one or more data
byte(s) read out from one of the CMX7131/CMX7141’s Read Only Registers, as shown in Figure 15.
Data sent from the µC on the CDATA (Command Data) line is clocked into the CMX7131/CMX7141 on the
rising edge of the SCLK (Serial Clock) input. RDATA (Reply Data) sent from the CMX7131/CMX7141 to
the µC is valid when SCLK is high. The CSN line must be held low during a data transfer and kept high
between transfers. The C-BUS interface is compatible with most common µC serial interfaces and may
also be easily implemented with general purpose µC I/O pins controlled by a simple software routine.
2014 CML Microsystems Plc
Page 30
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