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CMX7131Q1 参数 Datasheet PDF下载

CMX7131Q1图片预览
型号: CMX7131Q1
PDF下载: 下载PDF文件 查看货源
内容描述: [Microprocessor, 4MHz, CMOS, VQFN-64]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 4034 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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Digital PMR Radio Processor  
CMX7131/CMX7141  
CMX7131 CMX7141  
Pin  
Name  
Type  
64-pin  
Q1/L9  
48-pin  
Q3/L4  
Description  
Alternate input amplifier feedback  
19  
20  
21  
22  
23  
24  
ALTFB  
MICFB  
MIC  
OP  
OP  
IP  
27  
28  
29  
30  
31  
32  
Microphone input amplifier feedback  
Microphone inverting input  
AVSS  
MOD1  
MOD2  
PWR Analogue ground  
OP  
OP  
Modulator 1 output  
Modulator 2 output  
Internally generated bias voltage of about AV /2, except  
DD  
when the device is in ‘Powersave’ mode when VBIAS will  
25  
VBIAS  
OP  
discharge to AVSS. Must be decoupled to AV by a  
33  
SS  
capacitor mounted close to the device pins. No other  
connections allowed.  
26  
27  
28  
29  
30  
AUDIO  
ADC1  
ADC2  
ADC3  
ADC4  
OP  
IP  
Audio Output in SPI-Codec mode  
34  
35  
36  
37  
38  
Each of the two ADC blocks  
can select its input signal  
from any one of these input  
pins, or from the MIC, ALT or  
DISC input pins. See section  
8.1.3 for details.  
Auxiliary ADC input 1  
Auxiliary ADC input 2  
Auxiliary ADC input 3  
Auxiliary ADC input 4  
IP  
IP  
IP  
Analogue +3.3V supply rail. Levels and thresholds within the  
device are proportional to this voltage. This pin should be  
39  
31  
AVDD  
PWR  
decoupled to AV by capacitors mounted close to the  
SS  
device pins.  
40  
41  
42  
43  
44  
-
32  
33  
34  
35  
36  
37  
DAC1  
DAC2  
AVSS  
DAC3  
DAC4  
DVSS  
OP  
OP  
Auxiliary DAC output 1/RAMDAC  
Auxiliary DAC output 2  
PWR Analogue ground  
OP  
OP  
Auxiliary DAC output 3  
Auxiliary DAC output 4  
PWR Digital ground  
Internally generated 2.5V supply voltage. Must be decoupled  
to DV by capacitors mounted close to the device pins. No  
other connections allowed, except for the optional connection  
SS  
45  
38  
VDEC  
PWR  
to RFVDD  
.
46  
47  
39  
40  
XTAL/CLK  
XTALN  
IP  
Input from the external clock source or Xtal  
The output of the on-chip Xtal oscillator inverter.  
NC if external clock used.  
OP  
Digital +3.3V supply rail. This pin should be decoupled to  
DVSS by capacitors mounted close to the device pins.  
48  
49  
41  
42  
DVDD  
PWR  
IP  
CDATA  
C-BUS Command Data: Serial data input from the µC  
C-BUS Reply Data: A 3-state C-BUS serial data output to the  
43  
RDATA  
-
TS OP µC. This output is high impedance when not sending data to  
the µC.  
50  
51  
-
NC  
Reserved do not connect this pin  
2014 CML Microsystems Plc  
Page 9  
D/7141_FI-3.x/6  
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