Digital PMR Radio Processor
CMX7131/CMX7141
3
Signal List
CMX7131 CMX7141
Pin
Name
Type
64-pin
Q1/L9
48-pin
Q3/L4
Description
C-BUS: A 'wire-ORable' output for connection to the Interrupt
Request input of the host. Pulled down to DV when active
and is high impedance when inactive. An external pull-up
resistor (R1) is required.
SS
8
IRQN
OP
1
-
-
-
-
-
RF1N
RF1P
IP
IP
RF Synthesiser 1 negative input
RF Synthesiser 1 positive input
2
3
4
5
6
RFVSS
CP1OUT
ISET1
PWR The negative supply rail (ground) for RF Synthesiser 1
OP
IP
RF Synthesiser 1 Charge Pump output
RF Synthesiser 1 Charge Pump Current Set input
The 2.5V positive supply rail for both RF Synthesisers. This
-
RFVDD
PWR should be decoupled to RFV
close to the device pins.
by a capacitor mounted
7
SS
-
-
-
-
-
RF2N
RF2P
IP
IP
RF Synthesiser 2 negative input
RF Synthesiser 2 positive input
8
9
RFVSS
CP2OUT
ISET2
PWR The negative supply rail (ground) for RF Synthesiser 2
10
11
12
OP
IP
RF Synthesiser 2 Charge Pump output
RF Synthesiser 2 Charge Pump Current Set input
The 3.3V positive supply rail for the RF Synthesiser charge
-
CPVDD
PWR pumps. This should be decoupled to RFV by a capacitor
SS
13
mounted close to the device pins.
1
-
RFCLK
GPIOA
GPIOB
-
IP
14
15
16
17
RF Clock Input (common to both RF Synthesisers)
11
12
-
OP
OP
NC
General purpose I/O pin
General purpose I/O pin
Reserved – do not connect this pin
Internally generated 2.5V digital supply voltage. Must be
decoupled to DV by capacitors mounted close to the
device pins. No other connections allowed, except for
SS
9
VDEC
PWR
18
optional connection to RFV
.
DD
10
13
14
-
RXENA
SYSCLK1
DVSS
-
OP
OP
Rx Enable – active low when in Rx mode ($C1:b0 = 1)
19
20
21
22
23
24
25
26
Synthesised Digital System Clock Output 1
PWR Digital ground
NC
OP
IP
Reserved – do not connect this pin
15
16
17
18
TXENA
DISC
Tx Enable – active low when in Tx mode ($C1:b1 = 1)
Discriminator inverting input
DISCFB
ALT
OP
IP
Discriminator input amplifier feedback
Alternate inverting input
1
To minimise crosstalk, this signal should be connected to the same clock source as XTAL/CLK input.
2014 CML Microsystems Plc
Page 8
D/7141_FI-3.x/6
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