AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
CMX7032 CMX7042
Signal
Type
64-pin
Q1/L9
48-pin
Q3/L4
Description
Name
RX1N
RX1FB
RX2N
IP
OP
IP
Rx1 inverting input.
24
25
26
27
28
29
30
31
32
16
17
18
19
20
21
22
23
24
Rx1 input amplifier feedback.
Rx2 inverting input.
RX2FB
SpareFB
SpareN
AVSS
OP
OP
IP
Rx2 input amplifier feedback.
Spare input amplifier feedback.
Spare inverting input.
PWR Analogue Ground.
MOD1
MOD2
OP
OP
Modulator 1 output.
Modulator 2 output.
Internally generated bias voltage of about AV /2, except
DD
when the device is in ‘Powersave’ mode when V
will
BIAS
VBIAS
OP
discharge to AV . Must be decoupled to AV by a
SS SS
33
25
capacitor mounted close to the device pins. No other
connections allowed.
-
NC
IP
Reserved – do not connect this pin.
Analogue RSSI input from Limiter / Discriminator 1.
Analogue RSSI input from Limiter / Discriminator 2.
ADC input 1.
34
35
36
37
38
26
27
28
29
30
RSSI1
RSSI2
ADC1
ADC2
IP
IP
IP
ADC input 2.
Analogue +3.3V supply rail. Levels and thresholds within the
device are proportional to this voltage. This pin should be
39
31
AVDD
PWR
decoupled to AV by capacitors mounted close to the
SS
device pins.
40
41
42
43
44
-
32
33
34
35
36
37
DAC1
DAC2
AVSS
DAC3
DAC4
DVSS
OP
OP
DAC output 1/RAMDAC.
DAC output 2.
PWR Analogue Ground.
OP
OP
DAC output 3.
DAC output 4.
PWR Digital Ground.
Internally generated 2.5V supply voltage. Must be decoupled
to DV by capacitors mounted close to the device pins. No
SS
other connections allowed, except for the optional
45
38
VDEC
PWR
connection to RFV
.
DD
19.2MHz input from the external clock source or 9.6MHz
Xtal.
46
47
39
40
XTAL/CLK
XTALN
IP
The output of the on-chip 9.6MHz Xtal oscillator inverter. NC
if 19.2MHz Clock used.
OP
Digital +3.3V supply rail. This pin should be decoupled to
48
49
41
42
DVDD
PWR
IP
DV by capacitors mounted close to the device pins.
SS
CDATA
C-BUS: Command Data. Serial data input from the µC.
2012 CML Microsystems Plc
9
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
