CMX7042Q3 参数 Datasheet PDF下载

AIS Baseband IC with/without RF Synthesiser

CMX7032/CMX7042

3

Signal List

CMX7032 CMX7042

64-pin

48-pin

Q1/L9

Q3/L4

Signal

Name

Type

Description

C-BUS: A 'wire-ORable' output for connection to the

Interrupt Request input of the host. Pulled down to DV

SS

when active and is high impedance when inactive. An

external pull-up resistor (R1) is required.

RF Synthesiser #1 Negative input.

RF Synthesiser #1 Positive input.

The negative supply rail (ground) for the RF synthesisers.

1st Charge Pump output.

1st Charge Pump Current Set input.

The 2.5V positive supply rail for the RF synthesisers. This

should be decoupled to RFV

SS

by a capacitor mounted

close to the device pins.

RF Synthesiser #2 Negative input.

RF Synthesiser #2 Positive input.

The negative supply rail (ground) for the 2nd RF

synthesiser.

2nd Charge Pump output.

2nd Charge Pump Current Set input.

The 3.3V positive supply rail for the RF charge pumps. This

should be decoupled to RFV

SS

by a capacitor mounted

close to the device pins.

RF Clock Input (common to both synthesisers)

1

.

Pulse output when device is about to Tx.

Internal SlotCLK output

Reserved – do not connect this pin.

Internally generated 2.5V digital supply voltage. Must be

decoupled to DV

SS

by capacitors mounted close to the

device pins. No other connections allowed, except for

optional connection to RFV

DD

.

Slot Clock from host (37.5Hz).

Pulse output when device is about to Tx.

Internal SlotCLK output

Synthesised Digital System Clock Output 1.

Digital Ground.

Reserved – do not connect this pin.

Enable for external Tx hardware.

1

8

IRQN

OP

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

RF1N

RF1P

RFVSS

CP1OUT

ISET1

RFVDD

RF2N

RF2P

RFVSS

CP2OUT

ISET2

CPVDD

RFCLK

CS-SYNC

SLOTCLKOP

-

IP

IP

PWR

OP

IP

PWR

IP

IP

PWR

OP

IP

PWR

IP

OP

OP

NC

18

9

VDEC

PWR

19

-

-

20

21

22

23

1

10

11

12

13

14

-

15

SLOTCLK

CS-SYNC

SLOTCLKOP

SYSCLK1

DVSS

-

TXENA

IP

OP

OP

OP

PWR

NC

OP

To minimise crosstalk, this signal should be connected to the same clock source as XTAL/CLK input. By

default, this is connected internally at power-on, alternatively, this may be achieved by connecting the pin

to the XTALN output when a 19.2MHz source is in use.



2012 CML Microsystems Plc

8

D/7032/42_FI1.2/13