AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
3
Signal List
CMX7032 CMX7042
Signal
Name
Type
64-pin
Q1/L9
48-pin
Q3/L4
Description
C-BUS: A 'wire-ORable' output for connection to the
Interrupt Request input of the host. Pulled down to DV
when active and is high impedance when inactive. An
external pull-up resistor (R1) is required.
SS
IRQN
OP
1
8
RF1N
RF1P
IP
IP
RF Synthesiser #1 Negative input.
RF Synthesiser #1 Positive input.
2
3
4
5
6
-
-
-
-
-
RFVSS
CP1OUT
ISET1
PWR The negative supply rail (ground) for the RF synthesisers.
OP
IP
1st Charge Pump output.
1st Charge Pump Current Set input.
The 2.5V positive supply rail for the RF synthesisers. This
RFVDD
PWR should be decoupled to RFV by a capacitor mounted
7
-
SS
close to the device pins.
RF2N
RF2P
IP
IP
RF Synthesiser #2 Negative input.
RF Synthesiser #2 Positive input.
8
9
-
-
The negative supply rail (ground) for the 2nd RF
synthesiser.
RFVSS
PWR
10
-
CP2OUT
ISET2
OP
IP
2nd Charge Pump output.
11
12
-
-
2nd Charge Pump Current Set input.
The 3.3V positive supply rail for the RF charge pumps. This
CPVDD
PWR should be decoupled to RFV by a capacitor mounted
13
-
SS
close to the device pins.
1
RFCLK
CS-SYNC
SLOTCLKOP
-
IP
14
15
16
17
-
-
-
-
RF Clock Input (common to both synthesisers) .
OP
OP
NC
Pulse output when device is about to Tx.
Internal SlotCLK output
Reserved – do not connect this pin.
Internally generated 2.5V digital supply voltage. Must be
decoupled to DV by capacitors mounted close to the
device pins. No other connections allowed, except for
SS
VDEC
PWR
18
9
optional connection to RFV
.
DD
SLOTCLK
CS-SYNC
SLOTCLKOP
SYSCLK1
DVSS
IP
Slot Clock from host (37.5Hz).
19
-
10
11
12
13
14
-
OP
OP
OP
Pulse output when device is about to Tx.
Internal SlotCLK output
-
Synthesised Digital System Clock Output 1.
20
21
22
23
PWR Digital Ground.
-
NC
OP
Reserved – do not connect this pin.
Enable for external Tx hardware.
TXENA
15
1
To minimise crosstalk, this signal should be connected to the same clock source as XTAL/CLK input. By
default, this is connected internally at power-on, alternatively, this may be achieved by connecting the pin
to the XTALN output when a 19.2MHz source is in use.
2012 CML Microsystems Plc
8
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
