AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
CMX7032 CMX7042
Signal
Type
64-pin
Q1/L9
48-pin
Q3/L4
Description
C-BUS: Reply Data. A 3-state C-BUS serial data output to
Name
RDATA
TS OP the µC. This output is high impedance when not sending
data to the µC.
50
43
51
52
53
54
55
56
57
58
59
60
61
44
45
-
-
DVSS
NC
Reserved – do not connect this pin.
PWR Digital Ground.
-
NC
IP
Reserved – do not connect this pin.
SCLK
C-BUS: The C-BUS serial clock input from the µC.
Synthesised Digital System Clock Output 2.
C-BUS: The C-BUS chip select input from the µC.
46
47
48
-
SYSCLK2
CSN
OP
IP
CBUSMODE
EPSI
IP+PD Reserved – connect to DV (CMX7032 only).
SS
1
OP
OP
Serial Memory Interface:SPI bus Output.
Serial Memory Interface:SPI bus Clock.
2
EPSCLK
EPSO
3
IP+PD Serial Memory Interface:SPI bus Input.
4
EPSCSN
OP
Serial Memory Interface:SPI bus Chip Select.
Used in conjunction with BOOTEN2 to determine the
operation of the bootstrap program.
62
5
BOOTEN1
IP+PD
Used in conjunction with BOOTEN1 to determine the
operation of the bootstrap program.
63
64
6
7
BOOTEN2
DVSS
IP+PD
PWR Digital Ground.
On Q1 and Q3 packages only, the central metal pad may be
EXPOSED
METAL
PAD
EXPOSED
METAL
PAD
connected to Analogue Ground (AV ) or left unconnected.
SS
SUB
~
No other electrical connection is permitted.
Notes:
IP
OP
TS OP
PWR
NC
=
=
=
=
=
Input (+PU/PD = internal pullup/pulldown resistor)
Output
3-state Output
Power Supply Connection
No Connection
Functions with no associated pin number are not available in the CMX7042.
SLOTCLKOP and CS-SYNC functions are not available on CMX7032 devices with
batch codes before #72181.
2012 CML Microsystems Plc
10
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
