AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
Notes:
21
22
25
26
Tamb = 25°C, not including any current drawn from the device pins by external circuitry.
RF and auxiliary circuits disabled.
Characteristics when driving the XTAL/CLK pin with an external clock source.
Applies when utilising V
to provide a reference voltage to other parts of the system.
BIAS
When using V
as a reference, V
must be buffered. V
must always be decoupled
BIAS
BIAS
BIAS
with a capacitor as shown in Figure 4.
31
34
35
36
37
41
Timing for an external input to the XTAL/CLK pin.
With no external components connected, measured at dc.
After multiplying by gain of input circuit, with external components connected.
Gain applied to signal at output of buffer amplifier:RX1FB, RX2FB or SpareFB.
Design Value. Overall attenuation input to output has a tolerance of 0dB ±1.0dB.
Power-up refers to issuing a C-BUS command to turn on an output. These limits apply only if
V
BIAS
is on and stable.
42
43
44
51
Small signal impedance, at AV = 3.3V and Tamb = 25°C.
With respect to the signal at the feedback pin of the selected input port.
DD
With the output driving a 20k load to AV /2.
DD
Denotes output impedance of the driver of the auxiliary input signal,
to ensure <1 bit additional error under nominal conditions.
53
61
62
63
64
Guaranteed monotonic with no missing codes.
Sine wave or clipped sine wave.
Separate dividers provided for each PLL.
External ISET resistor (R31) = 0Ω (Internal ISET resistor = 9k6Ω nominally).
For optimum performance of the synthesiser subsystems, a common master clock should be
used for the RF Synthesisers and the baseband sections. Using unsynchronised clocks is
likely to result in spurious products being generated in the synthesiser outputs and in some
cases difficulty may be experienced in obtaining lock in the RF Synthesisers.
Operation outside these frequency limits is possible, but not guaranteed. Below 150MHz, a
square wave input may be required to provide a fast enough slew rate.
Lower input frequencies may be used subject to division ratio requirements being maintained.
It is recommended that RF Synthesiser 1 be used for higher frequency use
(eg: RF 1st LO) and RF Synthesiser 2 be used for lower frequency use (eg: IF LO).
1Hz Normalised Phase Noise Floor (PN1Hz) can be used to calculate the phase noise within
65
66
67
68
the PLL loop by: Phase Noise (in band) = PN1Hz + 20 log (N) + 10log (f
).
10
10 comparison
2012 CML Microsystems Plc
55
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
