AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
8.3 SPI Timing
Figure 20 SPI Interface Timing
Serial (SPI) Bus Interface Timing
Notes
Min.
Typ.
Max.
Unit
Xtal Clock
Periods
Xtal Clock
Periods
Xtal Clock
Periods
ns
t
t
t
Clock cycle time
–
16
–
–
–
CK
CL
CH
Clock 'low' pulse width
Clock 'high' pulse width
–
–
8
8
t
t
t
t
Out data valid time
Out data hold time
In data set up time
In data hold time
–
0
20
20
10
–
–
80
–
–
DOV
DOH
DS
ns
ns
ns
–
–
DH
Xtal Clock
Periods
Xtal Clock
Periods
t
Chip select low to clock rising edge
Clock falling edge to chip select high
–
–
4
2
–
–
CLC
CCH
t
1. The serial (SPI) bus clock frequency is the CMX7032/CMX7042 internal
Notes:
(Main Clock ÷ 16) frequency. At power-on, the internal Main Clock is connected directly
to the XTAL/CLK pin. A serial memory should be chosen which is compatible with these
timings.
2. Maximum 30pF load on each serial bus interface line.
2012 CML Microsystems Plc
58
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
