AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
A typical AIS transmission is shown in Figure 13. The CMX7032/CMX7042 starts timing relative to the
rising edge of SLOTCLK. At the end of a transmission, a sequence of “power-down” actions is performed
which are timed relative to the last message bit having been modulated, shown as point B in Figure 13. In
this way differences in message length due to bit stuffing are automatically accommodated.
The relative timings of the transmit sequence events are configured as a table of values that are loaded
into the CMX7032/CMX7042 using a Config Task operation (User Manual section 9.19.2.7) – this
operation must be performed before any transmissions are attempted. Typically, this will only need to be
done once as part of an initialisation routine. All timings are measured in units of “ticks”, each of which
lasts for 1/24000Hz ( 41.666µs). There are 2.5 ticks per modulated bit.
The transmit sequence consists of two initial setting values followed by a number of different event types.
These are:
Initial delay from the SLOTCLK edge.
Initial state of the TXENA pin.
Changes to the external hardware, via the TXENA pin (typically used to turn the Tx on/off) and the
DAC1 ramp up/down.
Trigger for the start/end of the CSTDMA sensing period (if CSTDMA is enabled).
Timing triggers for the start and end of the data modulation.
A dummy event in case any of the above are not required in the application.
The transmit event sequence is programmed using a Config task, see User Manual section 9.19.2.7.
Table 7 Tx Sequence Events
b3
0
b2
0
b1
0
b0
0
EVENT ID
dummy
DECRIPTION
Do nothing
0
0
0
0
0
0
0
1
1
1
0
1
CSTDMA_START
CSTDMA_END
Tx_en_hi
Defines the start of the CSTDMA sensing window
Defines the end of the CSTDMA sensing window
Pin TXENA is set high
0
1
0
0
RAMDAC_UP
AuxDAC1 will start executing a Ramp up
0
1
0
1
MODULATE_START Defines the start of data modulation
0
1
1
0
MODULATE_END
Delay from the end of modulation (based on the last data bit loaded into
modem - includes a 30 tick delay for the internal filters)
AuxDAC1 will start executing a Ramp down
Pin TXENA is set low
0
1
1
1
0
0
1
0
0
1
0
1
RAMDAC_DOWN
Tx_en_lo
dummy
Do nothing
When calculating the MODULATE_START timing value, the delay through the CMX7032/CMX7042’s
internal transmit filters and any external components must be taken into account to ensure that data bits
appear on-air at the correct time (the filter delays are specified in section 8.1.4. The MODULATE_END
event has an in-built delay of 30 ticks to allow the last bit to make its way out of the transmit filter and
external components. Allowance must be made for this built-in delay, as well as for the delay through any
external components, when calculating the timing of the transmit power down events.
Further explanation of Figure 13 is given in Table 8 (the order of events and delay timings shown are for
illustrative purposes only).
2012 CML Microsystems Plc
36
D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
