AIS Baseband IC with/without RF Synthesiser
CMX7032/CMX7042
7.7.2 AIS Raw Mode Receive
The operation of receive channel Rx1 in AIS raw mode is described below (the operation of receive
channel Rx2 in AIS raw mode is essentially identical to that of Rx1, but is controlled through its own set of
tasks). Note that both channels operate in either Raw or Burst mode, it is not possible to select AIS Raw
mode on one channel and AIS Burst mode on the other.
In AIS raw mode, the Rx RAW bit in the Command register, $C8 must be set. The CMX7032/CMX7042
then searches the Rx1 channel for a header (training + start flag sequence) to detect the start of a
message, then transfers the three training bytes and the start flag to the Rx1 Data buffer. The number of
subsequent words transferred to the buffer is set by the value in the RxData Count register, which is read
whenever the RXR1 task is executed. R1BRDY bit will be set when the programmed number of words
have been transferred. The data can then be read back using Data Read tasks. A new RXR task should
then be executed if it is required to recover further data words. It is the responsibility of the µC to perform
all HDLC/NRZI decoding, CRC checking and end flag detection. The demodulated byte stream continues
even after the end of a message and in the absence of a received signal (the data will then be
indeterminate. Reception can be halted by issuing an AbortRx1/2 task.
Bit ordering of the received data in AIS raw mode is the same as in Tx AIS raw mode, i.e. the received bits
are packed into words most significant bit first. As the AIS message structure requires message bytes to
be transmitted least significant bit first, the µC must ensure that during the process of HDLC/NRZI
decoding that the resulting data are correctly reversed. Depending on the configuration of the remote
transmitter, one of four different types of NRZI encoded training bytes may be received – this situation
arises because the AIS specification allows a transmitter’s NRZI encoder to start in either of its two
quiescent states, and the pre-NRZI encoded training bytes can also be one of two different types ($55 or
$AA). Therefore, for any particular message, the three received training bytes in AIS raw mode will all be
either $33, $66, $99 or $CC, although the first few bits may be corrupted depending on the power-up
characteristics of the remote transmitter and local receiver circuits.
In AIS raw mode, whenever an Rx1 state reset is performed (by issuing an AbortRx1 task) the channel
state becomes Idle. This changes to Receiving when the first valid training sequence and start flag have
been detected, where it remains until another Rx1 state reset occurs.
In Raw mode a single Rx Data buffer is used, however it is 4 words longer than the equivalent Burst mode
buffer as it does not contain any burst information.
7.7.3 DSC Receive
Either the Rx1 or Rx2 channel can be configured for DSC reception. The CMX7032/CMX7042 first applies
6dB/octave de-emphasis to the received signal, then demodulates the resulting 1200 baud FSK data. Only
one of the channels at a time can be configured for DSC reception. DSC reception can operate in either
Raw or Formatted mode. Formatted mode will significantly reduce the amount of data transferred to the
host and simplify the host processing requirements. It is enabled by setting the Command register ($C8)
bit 6 to 1.
In Formatted mode, the CMX7032/CMX7042 modem will check the incoming bit stream for a valid
sequence of phasing characters (3x Rx, 2x Dx+ Rx or Dx + 2 x Rx) and then report any correctly decoded
characters to the host. The conversion from 10-bit “emitted signal” data to 7-bit characters as well as
resolution of the time-diversity error detection is handled by the modem. The characters are packed into
the 16-bit register as two 7 bit characters and an additional error indication bit (bits 15 and 7). In the case
where an odd number of characters has been received, the unused field will be reported as '0000000' and
the error bit set to 1.
In Raw mode, the received data is packed into 16-bit words for onward transmission to the µC. The
CMX7032/CMX7042 makes no attempt to perform dot pattern or data phasing detection, those functions
must be performed by the host µC. No attempt is made to correctly align data, it is simply packed into
words (most significant bit first) as it arrives. To select Raw mode, Command register ($C8) bit 6 should
be cleared to 0.
On entering DSC mode, the buffers should be flushed before starting DSC data can be received.
e.g. For Rx1 channel reception, the sequence of C-BUS commands would be:
2012 CML Microsystems Plc
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D/7032/42_FI1.2/13
CMLMICRO [ CML MICROCIRCUITS ]
