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CMX7031L9 参数 Datasheet PDF下载

CMX7031L9图片预览
型号: CMX7031L9
PDF下载: 下载PDF文件 查看货源
内容描述: [Modem, PQFP64, LQFP-64]
分类和应用: 电信电信集成电路
文件页数/大小: 50 页 / 3145 K
品牌: CMLMICRO [ CML MICROCIRCUITS ]
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AX.25 Modem  
CMX7031/CMX7041  
7.3.1 FI Loading from Host Controller  
The FI can be included into the host controller software build and downloaded into the  
CMX7031/CMX7041 at power-up over the C-BUS interface. The BOOTEN pins must be set to the C-BUS  
load configuration, the CMX7031/CMX7041 powered up and placed into Program Mode, the data can then  
be sent directly over the C-BUS to the CMX7031/CMX7041.  
Each time the device is powered up its Function Image™ must first be loaded and then activated. These  
two steps assign internal device resources and determine all device features. The device does not  
operate until the Function Image™ is loaded and activated.  
BOOTEN2=1  
BOOTEN1=1  
Power-up / Reset CMX7031  
Send Start Block 1 Address (DB1_ptr) to C-BUS $B6  
Send Block 1Length (DB1_len) to C-BUS $B7  
Wait for C-BUS $C6 bit 0 to be set to 1  
Send $0001 to C-BUS $C8  
Wait for C-BUS $C6 bit 0 to be set to 1  
Send next data to C-BUS $C8  
Send Start Block 2 Address (DB2_ptr) to C-BUS $B6  
Send Block 2 Length (DB2_len) to C-BUS $B7  
Wait for C-BUS $C6 bit 0 to be set to 1  
Send $0001 to C-BUS $C8  
Wait for C-BUS $C6 bit 0 to be set to 1  
Send next data to C-BUS $C8  
Send Start Block 3 Address (ACTIVATE_ptr) to C-BUS $B6  
Send Block 3 Length (ACTIVATE_len) to C-BUS $B7  
Wait for C-BUS $C6 bit 0 to be set to 1  
Send $0001 to C-BUS $C8  
Wait for C-BUS $C6 bit 0 to be set to 1  
Verify Checksum values in $A9, $AA and  
$B8, $B9  
note: BOOTEN1 and  
BOOTEN2 may be changed  
at this point, if required  
Send Device Activation Code hi to $C8  
Wait for C-BUS $C6 bit 0 to be set to 1  
VDD  
Send Device Activation Code lo to $C8  
Wait for C-BUS $C6 bit 0 to be set to 1  
BOOTEN1  
BOOTEN2  
CMX7031 is now ready for use  
Figure 7 FI Loading from Host  
The download time is limited by the clock frequency of the C-BUS, with a 5MHz SCLK, it should take less  
than 500ms to complete.  
2013 CML Microsystems Plc  
Page 19  
D/7031/7041_FI-4.x/5  
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