AX.25 Modem
CMX7031/CMX7041
Note that once a particular mode (1200 or 9600) signal has been detected, the other demodulator is
switched off. Hence, after a data burst has been received by the host it should re-set both Modem Control
bits of the Mode register ($C1:b2,3) and then re-enable them (taking note of the C-BUS latency time).
In both GMSK and AFSK modes, a single bit error is allowed during the sync sequence detection.
7.6.2 Transmitting AFSK/GMSK Data
The CMX7031/CMX7041 will transmit all data transferred from the host over C-BUS at either 1200 or
9600bps as selected by the Mode Control register ($C1: b4,5).
The binary over-air data is taken from the device’s internal buffer which is loaded from the host using the
TxData register block, most significant bit first. The data must be provided over the C-BUS from the host
within certain time limits to ensure the selected baud rate is maintained and an underflow condition does
not occur. The device’s internal buffer is 256 bytes long and may be pre-loaded by the host before the Tx
Modulator is enabled. The host must supply ALL data to be transmitted, including any preamble that may
be required during the TxDelay period that precedes the actual data packet. The TxDataRDY flag will be
raised whenever there is room for a host to write a full TxData block. The TxDataRDY flag will be inhibited
when there are less than 4 bytes left empty in the buffer.
A Tx sequencer state machine is provided to automate the transmission of data bursts. The timings of the
sequencer can be pre-programmed by the host to suit the characteristics of the radio hardware. The
sequencer controls:
Table 4 TxSequencer Timing
ticks
0
ms
0
ms (cumulative)
0
TxENA active
Ramp Up Start Delay
Modulation Start Delay
240
240
10
20
10
30
…data will now be transmitted from the TxData block via the TxData buffer until the “Last Data” flag is
asserted by the host.
Ramp Down Start Delay
TxENA Inactive
240
240
10
10
10
20
All sequencer timing values are specified in terms of 24kHz “ticks”. Default values are shown in the tables.
The Modulation Start Delay allows for a period of un-modulated carrier to be output at the beginning of the
burst. The value chosen for this item should also take into account the time it takes for the RAMDAC to
complete its cycle (default is 10ms).
The Ramp Down Start Delay allows for a period of un-modulated carrier at the end of the burst if required.
The TxENA Inactive delay value chosen for this item should also take into account the time it takes for the
RAMDAC to complete its cycle (default is 10ms). Note that Program Register P3.0:b0 should be set to
enable RAMDAC operation.
2013 CML Microsystems Plc
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