AX.25 Modem
CMX7031/CMX7041
7
Detailed Descriptions
Xtal Frequency
7.1
The CMX7031/CMX7041 are designed to work with an external frequency source of 19.2MHz or a
12.4MHz Xtal. At power-on, a 19.2MHz source is selected by default. The 12.4MHz option can be selected
by setting the $C3 register appropriately whilst in Idle mode. The correct clock frequency MUST be
selected before the device is put into Rx or Tx mode.
7.2
Host Interface
A serial data interface (C-BUS) is used for command, status and data transfers between the
CMX7031/CMX7041 and the host µC; this interface is compatible with microwire, SPI. Interrupt signals
notify the host µC when a change in status has occurred and the µC should read the status register across
the C-BUS and respond accordingly. Interrupts only occur if the appropriate mask bit has been set. See
section 7.13.1.
The CMX7031/CMX7041 will monitor the state of the C-BUS registers that the host has written to every
50µs (the C-BUS latency period) hence it is not advisable for the host to make successive writes to the
same C-BUS register within this period.
To minimise activity on the C-BUS interface, optimise response times and ensure reliable data transfers, it
is advised that the IRQ facility be utilised (using the IRQ mask register, $CE). It is permissible for the host
to poll the IRQ pin if the host uC does not support a fully interrupt-driven architecture. This removes the
need to continually poll the C-BUS status register ($C6) for status changes.
7.2.1 C-BUS Operation
This block provides for the transfer of data and control or status information between the
CMX7031/CMX7041’s internal registers and the host µC over the C-BUS serial interface. Each transaction
consists of a single Address byte sent from the µC which may be followed by one or more Data byte(s)
sent from the µC to be written into one of the CMX7031/CMX7041’s Write-only registers, or one or more
data byte(s) read out from one of the CMX7031/CMX7041’s Read-only registers, as illustrated in Figure 6.
Data sent from the µC on the CDATA line is clocked into the CMX7031/CMX7041 on the rising edge of the
SCLK Clock input. RDATA sent from the CMX7031/CMX7041 to the µC is valid when the SCLK is high.
The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS
interface is compatible with most common µC serial interfaces and may also be easily implemented with
general purpose µC I/O pins controlled by a simple software routine.
The number of data bytes following an Address byte is dependent on the value of the Address byte. The
most significant bit of the address or data are sent first. For detailed timings see section 8.2. Note that,
due to internal timing constraints, there maybe a delay of up to 50s between the end of a C-BUS write
operation and the device reading the data from its internal register. When making multiple writes to the
same C-BUS location, ensure that the C-BUS latency period (typically 50µs) is observed.
2013 CML Microsystems Plc
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