EP9315
Enhanced Universal Platform SOC Processor
Ultra DMA Data Transfer
Figure 21 through Figure 30 define the timings associated with all phases of Ultra DMA bursts. The following table
contains the values for the timings for each of the Ultra DMA modes.
Timing reference levels = 1.5 V
Mode 0
Mode 1
Mode 2
Mode 3
(in ns)
(in ns)
(in ns)
(in ns)
Parameter
Symbol
min max min max min max min max
Cycle time allowing for asymmetry and clock variations
(from DSTROBE edge to DSTROBE edge)
tCYCRD
t2CYCRD
tCYCWR
t2CYCWR
112
230
230
460
-
-
-
-
73
-
-
-
-
54
-
-
-
-
39
86
-
-
-
-
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of DSTROBE)
154
170
340
115
130
260
Cycle time allowing for asymmetry and clock variations
(from HSTROBE edge to HSTROBE edge)
100
200
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of HSTROBE)
tDS
tDH
Data setup time at recipient (Read)
Data hold time at recipient (Read)
15
8
-
-
10
8
-
-
7
8
-
-
7
8
-
-
Data valid setup time at sender (Write)
(from data valid until STROBE edge)
(Note 2)
(Note2)
tDVS
tDVH
tFS
70
6
-
-
48
6
-
-
30
6
-
-
20
6
-
-
Data valid hold time at sender (Write)
(from STROBE edge until data may become invalid)
First STROBE time (for device to first negate DSTROBE from STOP
during a data in burst)
0
230
0
200
0
170
0
130
tLI
tMLI
tUI
Limited interlock time
(Note 3)
(Note 3)
(Note 3)
0
20
0
150
0
20
0
150
0
20
0
150
0
20
0
100
Interlock time with minimum
Unlimited interlock time
-
-
-
-
-
-
-
-
Maximum time allowed for output drivers to release
(from asserted or negated)
tAZ
-
10
-
10
-
10
-
10
tZAH
tZAD
Minimum delay time required for output
Drivers to assert or negate (from released)
20
0
-
-
20
0
-
-
20
0
-
-
20
0
-
-
Envelope time (from DMACKn to STOP and HDMARDYn during data in
burst initiation and from DMACKn to STOP during data out burst initiation)
tENV
tRFS
tRP
20
-
70
75
-
20
-
70
70
-
20
-
70
60
-
20
-
55
60
-
Ready-to-final-STROBE time (no STROBE edges shall be sent this long
after negation of DMARDYn)
Ready-to-pause time
(that recipient shall wait to pause after negating DMARDYn)
160
125
100
100
tIORDYZ
tZIORDY
tACK
Maximum time before releasing IORDY
-
20
-
-
20
-
-
20
-
-
20
-
Minimum time before driving STROBE
(Note 4)
0
0
0
0
Setup and hold times for DMACKn (before assertion or negation)
20
-
20
-
20
-
20
-
Time from STROBE edge to negation of DMARQ or assertion of STOP
(when sender terminates a burst)
tSS
50
-
50
-
50
-
50
-
Note: 1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies.
2. The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers. Timing for tDVS and tDVH shall be
met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
3. tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the
other to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited
time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.
4. tZIORDY may be greater than tENV since the device has a pull up on IORDYn giving it a known state when released.
5. All IDE timing is based upon HCLK = 100 MHz.
36
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