EP9315
Enhanced Universal Platform SOC Processor
Static Memory Single Word Write Cycle
Parameter
Symbol
Min
Typ
Max
Unit
tADs
-
AD setup to WRn assert time
-
ns
tHCLK -3
tADh
tCSh
tHCLK × 2
AD hold from WRn deassert time
WRn deassert to CSn deassert time
CSn to WRn assert delay time
WRn assert time
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
7
tWRd
tWRpw
tDQMd
tDAh
-
-
2
-
tHCLK × (WST1 + 1)
-
-
CSn to DQMn assert delay time
WRn deassert to DA transition time
WRn assert to DA valid
-
-
1
-
tHCLK
tDAV
-
-
8
tADs
tADh
AD
tCSh
CSn
tWRd
tWRpw
WRn
RDn
tDQMd
DQMn
tDAV
tDAh
DA
WAIT
Figure 7. Static Memory Single Word Write Cycle Timing Measurement
20
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