CS8900A
Crystal LAN™ Ethernet Controller
tometer useful in locating cable faults. The
following sections contain more information
about these counters.
Table 14 provides a summary of PacketPage
Register types.
Suffix
CMD
CFG
Type
Description
Comments
Read/Write
Read/Write
Command: Written once per frame to initiate transmit.
Configuration: Written at setup and used to determine
what frames will be transmitted and received and what
events will cause interrupts.
CTL
Read/Write
Control: Written at setup and used to determine what
frames will be transmitted and received and how the physi-
cal interface will be configured.
Event
ST
Read-only
Read-only
Read-only
Event: Reports the status of transmitted and received
frames.
cleared when read
cleared when read
Status: Reports information about the configuration of the
CS8900A.
Counters: Counts missed receive frames and collisions.
Provides time domain for locating coax cable faults.
Table 14. PacketPage Register Types
4.4.3 Status and Control Bit Definitions
vent, Bit B). Like all Event bits, RxDest and
Rx128 are cleared when read by the host.
This section provides a description of the spe-
cial bit types used in the Status and Control
registers. Section 4.4.4 on page 51 provides a
detailed description of the bits in each register.
4.4.3.3 Interrupt Enable Bits and Events
Interrupt Enable bits end with the suffix iE and
are located in three Configuration registers:
RxCFG (Register 3), TxCFG (Register 7), and
BufCFG (Register B). Each Interrupt Enable
bit corresponds to a specific event. If an Inter-
rupt Enable bit is set and its corresponding
event occurs, the CS8900A generates an in-
terrupt to the host processor.
4.4.3.1 Act-Once Bits
There are four bits that cause the CS8900A to
take a certain action only once when set.
These “Act-Once” bits are: Skip_1 (Register 3,
RxCFG, Bit 6), RESET (Register 15, SelfCTL,
Bit 6), ResetRxDMA (Register 17, BusCTL, Bit
6), and SWint-X (Register B, BufCFG, Bit 6).
To cause the action again, the host must set
the bit again. Act-Once bits are always read as
clear.
The bits that report when various events occur
are located in three Event registers and two
counters. The Event registers are RxEvent
(Register 4), TxEvent (Register 8), and BufE-
vent (Register C). The counters are RxMISS
(Register 10) and TxCOL (Register 12). Each
Interrupt Enable bit and its associated Event
are identified in Table 15.
4.4.3.2 Temporal Bits
Temporal bits are bits that are set and cleared
by the CS8900A without intervention of the
host processor. This includes all status bits in
the three status registers (Register 14, Lin-
eST; Register 16, SelfST; and, Register 18,
BusST), the RxDest bit (Register C, BufEvent,
Bit F), and the Rx128 bit (Register C, BufE-
An Event bit will be set whenever the specified
event happens, whether or not the associated
Interrupt Enable bit is set. All Event registers
are cleared upon read-out by the host.
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