CS8900A
Crystal LAN™ Ethernet Controller
4.4 Status and Control Registers
The Transmit Command Register (TxCMD) is
a special type of register. It appears in two
separate locations in the PacketPage memory
map. The first location, PacketPage base +
0108h, is within the block of Configura-
tion/Control Registers and is read-only. The
second location, PacketPage base + 0144h, is
where the actual transmit commands are is-
sued and is write-only. See Section 4.4.4 on
page 51 (Register 9) and Section 5.6 on
page 99 for a more detailed description of the
TxCMD register.
The Status and Control registers are the pri-
mary registers used to control and check the
status of the CS8900A. They are organized
into two groups: Configuration/Control Regis-
ters and Status/Event Registers. All Status
and Control Registers are 16-bit words as
shown in Figure 16. Bit 0 indicates whether it
is a Configuration/Control Register (Bit 0 = 1)
or a Status/Event Register (Bit 0 = 0). Bits 0
through 5 provide an internal address code
that describes the exact function of the regis-
ter. Bits 6 through F are the actual Configura-
tion/Control and Status/Event bits.
4.4.2 Status and Event Registers
Status and Event registers report the status of
transmitted and received frames, as well as in-
formation about the configuration of the
CS8900A. They are read-only and are desig-
nated by even numbers (e.g. Register 2, Reg-
ister 4, etc.).
4.4.1 Configuration and Control Registers
Configuration and Control registers are used
to setup the following:
•
•
•
•
how frames will be transmitted and re-
ceived;
The Interrupt Status Queue (ISQ) is a special
type of Status/Event register. It is located at
PacketPage base + 0120h and is the first reg-
ister the host reads when responding to an In-
terrupt.
which frames will be transmitted and re-
ceived;
which events will cause interrupts to the
host processor; and,
how the Ethernet physical interface will be
configured.
A more detailed description of the ISQ can be
found in Section 5.1 on page 78.
These registers are read/write and are desig-
nated by odd numbers (e.g. Register 1, Regis-
ter 3, etc.).
Three 10-bit counters are included with the
Status and Event registers. RxMISS counts
missed receive frames, TxCOL counts trans-
mit collisions, and TDR is a time domain reflec-
16-bit Register W ord
Bit Number
E
D
C
B
A
F
9
8
7
6
5
4
3
2
1
0
Internal Address
(bits 0 - 5)
1 = Control/C onfiguration
0 = Status/Event
10 R egister Bits
Figure 16. Status and Control Register Format
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