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CS8900A-IQZ 参数 Datasheet PDF下载

CS8900A-IQZ图片预览
型号: CS8900A-IQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 微控制器和处理器串行IO控制器通信控制器外围集成电路PC局域网以太网时钟
文件页数/大小: 138 页 / 2374 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ Ethernet Controller  
the CS8900A when the frame data are placed  
in either on-chip memory, or in host memory  
by DMA.) Four of these bits have correspond-  
ing Interrupt Enable (iE) bits. An Accept bit and  
an Interrupt Enable bit are independent opera-  
tions. It is possible to set either, neither, or  
both bits. The four corresponding pairs of bits  
are:  
Interrupt Enable Bit  
(register name)  
Event Bit or Counter  
(register name)  
ExtradataiE (RxCFG)  
RuntiE (RxCFG)  
Extradata (RxEvent)  
Runt (RxEvent)  
CRCerroriE (RxCFG)  
RxOKiE (RxCFG)  
CRCerror (RxEvent)  
RxOK (RxEvent)  
16colliE (TxCFG)  
AnycolliE (TxCFG)  
16coll (TxEvent)  
IE Bit in RxCFG  
ExtradataiE  
RuntiE  
A Bit in RxCTL  
ExtradataA  
RuntA  
“Number-of Tx-collisions”  
counter is incremented  
(TxEvent)  
JabberiE (TxCFG)  
Jabber (TxEvent)  
CRCerroriE  
RxOKiE  
CRCerrorA  
RxOKA  
Out-of-windowiE (TxCFG) Out-of-window (TxEvent)  
TxOKiE (TxCFG)  
SQEerroriE (TxCFG)  
Loss-of-CRSiE (TxCFG)  
TxOK (TXEvent)  
SQEerror (TxEvent)  
Loss-of-CRS (TxEvent)  
If one of the above Interrupt Enable bits is set  
and the corresponding Accept bit is clear, the  
CS8900A generates an interrupt when the as-  
sociated receive event occurs, but then does  
not accept the receive frame (the length of the  
receive frame is set to zero).  
MissOvfloiE (BufCFG)  
RxMISS counter over-  
flows past 1FFh  
TxColOvfloiE (BufCFG) TxCOL counter overflows  
past 1FFh  
The other five Accept bits in RxCTL are used  
for destination address filtering (see  
Section 5.2.10 on page 87). The Accept  
mechanism is explained in more detail in  
Section 5.2 on page 78.  
RxDestiE (BufCFG)  
Rx128iE (BufCFG)  
RxDest (BufEvent)  
Rx128 (BufEvent)  
RxMissiE (BufCFG)  
TxUnderruniE (BufCFG)  
Rdy4TxiE (BufCFG)  
RxDMAiE (BufCFG)  
RxMISS (BufEvent)  
TxUnderrun (BufEvent)  
Rdy4Tx (BufEvent)  
RxDMAFrame (BufEvent)  
4.4.4 Status and Control Register Sum-  
mary  
Table 15. Interrupt Enable Bits and Events  
4.4.3.4 Accept Bits  
The table on the following page (Table 16) pro-  
vides a summary of the Status and Control  
registers. Section 4.4.4 on page 51 gives a de-  
tailed description of each Status and Control  
register.  
There are nine Accept bits located in the Rx-  
CTL register (Register 5), each of which is fol-  
lowed by the suffix A. Accept bits indicate  
which types of frames will be accepted by the  
CS8900A. (A frame is said to be “accepted” by  
CIRRUS LOGIC PRODUCT DATASHEET  
DS271F4  
51  
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