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CS8900A-IQ 参数 Datasheet PDF下载

CS8900A-IQ图片预览
型号: CS8900A-IQ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
3.8 LED Outputs  
host, BSTATUS is low whenever the HCB1 bit  
(Register 15, SelfCTL, Bit F) is set. To configure it  
for host control, HC1E must be set. Table 10 sum-  
marizes this operation.  
The CS8900A provides three output pins that can  
be used to control LEDs or external logic.  
3.8.0.1 LANLED  
HC1E HCB1  
(Bit D) (Bit F)  
Pin Function  
LANLED goes low whenever the CS8900A trans-  
mits or receives a frame, or when it detects a colli-  
sion. LANLED remains low until there has been no  
activity for 6 ms (i.e. each transmission, reception,  
or collision produces a pulse lasting a minimum of  
6 ms).  
0
N/A  
Pin configured as BSTATUS: Output is  
low when a receive frame begins trans-  
fer across the ISA bus. Output is high  
otherwise  
1
1
0
1
Pin configured as HC1:  
Output is high  
3.8.0.2 LINKLED or HC0  
Pin configured as HC1:  
Output is low  
LINKLED or HC0 can be controlled by either the  
CS8900A or the host. When controlled by the  
CS8900A, LINKLED is low whenever the  
CS8900A receives valid 10BASE-T link pulses. To  
configure this pin for CS8900A control, the HC0E  
bit (Register 15, SelfCTL, Bit C) must be clear.  
When controlled by the host, LINKLED is low  
whenever the HCB0 bit (Register 15, SelfCTL, Bit  
E) is set. To configure it for host control, the HC0E  
bit must be set. Table 9 summarizes this operation.  
Table 10. BSTATUS/HCI Pin Operation  
3.8.1 LED Connection  
Each LED output is capable of sinking 10 mA to  
drive an LED directly through a series resistor. The  
output voltage of each pin is less than 0.4 V when  
the pin is low. Figure 7 shows a typical LED cir-  
cuit.  
+5V  
HC0E HCB0  
(Bit C) (Bit E)  
Pin Function  
0
N/A  
Pin configured as LINKLED: Output is  
low when valid 10BASE-T link pulses  
are detected. Output is high if valid link  
pulses are not detected  
LANLED  
1
1
0
1
Pin configured as HC0:  
Output is high  
Pin configured as HC0:  
Output is low  
LINKLED  
Figure 7. LED Connection Diagram  
Table 9. LINKLED/HC0 Pin Operation  
3.8.0.3 BSTATUS or HC1  
3.9 Media Access Control  
BSTATUS or HC1 can be controlled by either the  
CS8900A or the host. When controlled by the  
CS8900A, BSTATUS is low whenever the host  
reads the RxEvent register (PacketPage base +  
0124h), signaling the transfer of a receive frame  
across the ISA bus. To configure this pin for  
CS8900A control, the HC1E bit (Register 15, Self-  
CTL, Bit D) must be clear. When controlled by the  
3.9.1 Overview  
The CS8900A’s Ethernet Media Access Control  
(MAC) engine is fully compliant with the IEEE  
802.3 Ethernet standard (ISO/IEC 8802-3, 1993). It  
handles all aspects of Ethernet frame transmission  
and reception, including: collision detection, pre-  
amble generation and detection, and CRC genera-  
CIRRUS LOGIC PRODUCT DATA SHEET  
28  
DS271PP3  
 
 
 
 
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