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CS8900A-IQ 参数 Datasheet PDF下载

CS8900A-IQ图片预览
型号: CS8900A-IQ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
BootPROM Address Mask register (PacketPage  
dicating that the EEPROM is no longer being read  
base + 0034h). The Boot PROM Base Address pro- or programmed. Time required for the reset calibra-  
vides the starting location in host memory where tion is typically 10 ms. Software drivers should not  
the Boot PROM is mapped. The Boot PROM Ad- access registers internal to CS8900A during this  
dress Mask indicates the size of the attached Boot  
PROM and is limited to 4-Kbyte increments. The  
lower 12 bits of the Address Mask are ignored and  
should be 000h.  
time.  
3.7.1 Hardware Standby  
Hardware (HW) Standby is designed for use in sys-  
tems, such as portable PC’s, that may be temporari-  
ly disconnected from the 10BASE-T cable. It  
allows the system to conserve power while the  
LAN is not in use, and then automatically restore  
Ethernet operation once the cable is reconnected.  
CS8900A  
CSOUT  
(Pin 17)  
27C256  
CE  
OE  
74LS245  
OE  
20  
22  
19  
DIR  
In HW Standby mode, all analog and digital cir-  
cuitry in the CS8900A is turned off, except for the  
10BASE-T receiver which remains active to listen  
for link activity. If link activity is detected, the  
LANLED pin is driven low, providing an indica-  
tion to the host that the network connection is ac-  
tive. The host can then activate the CS8900A by  
deasserting the SLEEP pin. During this mode, all  
ISA bus accesses are ignored.  
A1  
.
.
.
B1  
.
.
ISA  
BUS  
SA(0:14)  
SD(0:7)  
A8  
.
B8  
Figure 6. Boot PROM Connection Diagram  
In the EEPROM example shown in Table 6, the  
Boot PROM starting address is D0000h and the  
Address Mask is FC000h. This configuration de-  
scribes a 16-Kbyte (128 Kbit) PROM mapped into  
host memory from D0000h to D3FFFh.  
To enter HW Standby mode, the SLEEP pin must  
be low and the HWSleepE bit (Register 15, Self-  
CTL, Bit 9) and the HWStandbyE bit (Register 15,  
SelfCTL, Bit A) must be set. When the CS8900A  
enters HW Standby, all registers and circuits are re-  
set except for the SelfCTL register. Upon exit from  
HW Standby, the CS8900A performs a complete  
reset, and then goes through normal initialization.  
3.7 Low-Power Modes  
For power-sensitive applications, the CS8900A  
supports three low-power modes: Hardware Stand-  
by, Hardware Suspend, and Software Suspend. All  
three low-power modes are controlled through the  
SelfCTL register (Register 15). See also  
Section 4.4.4 on page 49.  
3.7.2 Hardware Suspend  
During Hardware Suspend mode, the CS8900A  
uses the least amount of current of the three low-  
power modes. All internal circuits are turned off  
and the CS8900A’s core is electronically isolated  
from the rest of the system. Accesses from the ISA  
bus and Ethernet activity are both ignored.  
An internal reset occurs when the CS8900A comes  
out of any suspend or standby mode. After a reset  
(internal or external), the CS8900A goes through a  
self configuration. This includes calibrating on-  
chip analog circuitry, and reading EEPROM for va-  
lidity and configuration. When the calibration is  
done, bit InitD in Register 16 (Self Status register)  
is set indicating that initialization is complete, and  
the SIBUSY bit in the same register is cleared (in-  
HW Suspend mode is entered by driving the  
SLEEP pin low and setting the HWSleepE bit  
(Register 15, SelfCTL, bit 9) while the HWStand-  
byE bit (Register 15, SelfCTL, bit A) is clear. To  
CIRRUS LOGIC PRODUCT DATA SHEET  
26  
DS271PP3  
 
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