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CS8900A-IQ 参数 Datasheet PDF下载

CS8900A-IQ图片预览
型号: CS8900A-IQ
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
tion and test. Programmable MAC features include 1021 bytes, or full frame), and providing that ac-  
automatic retransmission on collision, and padding cess to the network is permitted, the MAC automat-  
of transmitted frames.  
ically transmits the 7-byte preamble (1010101b...),  
followed by the Start-of-Frame Delimiter (SFD,  
10101011b), and then the serialized frame data. It  
then transmits the Frame Check Sequence (FCS).  
The data after the SFD and before the FCS (Desti-  
nation Address, Source Address, Length, and data  
field) is supplied by the host. FCS generation by the  
CS8900A may be disabled by setting the Inhibit-  
CRC bit (Register 9, TxCMD, bit C).  
Figure 8 shows how the MAC engine interfaces to  
other CS8900A functions. On the host side, it inter-  
faces to the CS8900A’s internal data/address/con-  
trol bus. On the network side, it interfaces to the  
internal Manchester encoder/decoder (ENDEC).  
The primary functions of the MAC are: frame en-  
capsulation and decapsulation; error detection and  
handling; and, media access management.  
Figure 9 shows the Ethernet frame format.  
LED  
Logic  
3.9.2.2 Reception  
The MAC receives the incoming packet as a serial  
stream of NRZ data from the Manchester encod-  
er/decoder. It begins by checking for the SFD.  
Once the SFD is detected, the MAC assumes all  
subsequent bits are frame data. It reads the DA and  
compares it to the criteria programmed into the ad-  
dress filter (see Section 5.3 on page 87 for a de-  
scription of Address Filtering). If the DA passes the  
address filter, the frame is loaded into the  
CS8900A’s memory. If the BufferCRC bit (Regis-  
ter 3, RxCFG, bit B) is set, the received FCS is also  
loaded into memory. Once the entire packet has  
been received, the MAC validates the FCS. If an er-  
ror is detected, the CRCerror bit (Register 4, Rx-  
Event, Bit C) is set.  
Encoder/  
802.3  
MAC  
Decoder  
&
CS8900A  
Internal Bus  
10BASE-T  
& AUI  
Engine  
PLL  
Figure 8. MAC Interface  
3.9.2 Frame Encapsulation and Decapsulation  
The CS8900A’s MAC engine automatically as-  
sembles transmit packets and disassembles receive  
packets. It also determines if transmit and receive  
frames are of legal minimum size.  
3.9.2.1 Transmission  
Once the proper number of bytes have been trans-  
ferred to the CS8900A’s memory (either 5, 381,  
3.9.2.3 Enforcing Minimum Frame Size  
The MAC provides minimum frame size enforce-  
Packet  
Frame  
up to 7 bytes  
1 byte  
6 bytes  
6 bytes  
2 bytes  
4 bytes  
alternating 1s / 0s SFD  
DA  
SA  
Length Field LLC data  
Pad  
FCS  
preamble  
frame length  
min 64 bytes  
max 1518 bytes  
Direction of Transmission  
SFD = Start of Frame Delimiter  
DA = Destination Address  
SA = Source Address  
LLC = Logical Link Control  
FCS = Frame Check Sequence (also  
called Cyclic Redundancy Check, or CRC)  
Figure 9. Ethernet Frame Format  
CIRRUS LOGIC PRODUCT DATA SHEET  
DS271PP3  
29  
 
 
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