CS5510/11/12/13
SWITCHING CHARACTERISTICS - CS5511/13
(T = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; C = 50 pF)
A
L
Parameter
Symbol Min
Typ
Max
Unit
Internal Oscillator Timing
Internal Oscillator Frequency
(Note 23)
f
32
-
64
100
-
kHz
osc
Internal Oscillator Drift Over Temperature
Serial Port Timing
-
-0.02
%/°C
Serial Clock Frequency
SCLK High to Enter Sleep
SCLK Low to Exit Sleep
Rise Times
(Note 24) SCLK
-
-
-
-
2
2000
-
MHz
µs
(Notes 24 and 25)
t
200
10
SLP
(Notes 24 and 25) t
µs
WAKE
(Note 26)
CSB
t
rise
-
-
-
-
-
50
1.0
10
-
µs
µs
ns
SCLK
SDO
Fall Times
(Note 26)
CSB
t
fall
-
-
-
-
-
50
1.0
10
-
µs
µs
ns
SCLK
SDO
Serial Clock
Pulse Width High
Pulse Width Low
t
t
200
200
-
-
-
-
ns
ns
6
7
SDO Read Timing
t
t
-
-
150
ns
CS to Data Valid
8
SCLK Falling to New Data Bit
-
-
-
-
150
150
ns
ns
9
t
CS Rising to SDO Hi-Z
10
t
200
-
-
ns
CS Falling to SCLK Rising
11
Notes: 23. The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is
retrieved from the serial port using the SCLK input pin.
24. The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being
read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10
percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is
entered after SCLK is logic 1 for t
time.
SLP
25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held
high (logic 1) for t or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must
SLP
be held low (logic 0) for t
or longer.
WAKE
26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
8
DS337F3
CIRRUS [ CIRRUS LOGIC ]
