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CS5513-BS 参数 Datasheet PDF下载

CS5513-BS图片预览
型号: CS5513-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 16位和20位, 8引脚Σ-Δ型ADC [16-bit and 20-bit, 8-pin Sigma-Delta ADC]
分类和应用:
文件页数/大小: 24 页 / 408 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5510/11/12/13  
ferential voltage reference (VREF - V-). This trans-  
lates to typically 4.0 V fully differential when the  
reference voltage between VREF and V- is 5 V,  
and typically 2.0 V fully differential at 2.5 V.  
2. GENERAL DESCRIPTION  
The CS5510/11/12/13 are low-cost, easy-to-use,  
∆Σ analog-to-digital converters (ADCs) which use  
charge balance techniques to achieve 16-bit  
(CS5510/11) and 20-bit (CS5512/13) perfor-  
mance. The ADCs are available in a space-effi-  
cient, 8-pin, SOIC package and are optimized for  
measuring signals in weigh scale, process control,  
and other industrial applications.  
Note:  
When a smaller reference voltage is used,  
the resulting code widths are smaller. Since  
the output codes exhibit more changing  
codes for a fixed amount of noise, the  
converter appears noisier.  
2.1.1 Analog Input Model  
To accommodate these applications, the ADCs in-  
clude a fourth-order ∆Σ modulator and a digital fil-  
ter. When configured with an external master clock  
of 32.768 kHz, the filter in the CS5510/12 provides  
better than 80 dB of simultaneous 50 and 60 Hz  
line rejection, and outputs conversion words at  
53.5 Sps. The CS5511/13 include an on-chip oscil-  
lator which eliminates the need for an external  
clock source.  
Figure 3 illustrates the input model for the AIN  
pins. The model includes a coarse/fine charge  
buffer which reduces the dynamic current de-  
mands from the signal source. The buffer is de-  
signed to accommodate rail-to-rail (common-mode  
plus signal) input voltages. Typical CVF (sampling)  
current is about 10 nA. Application Note 30,  
“Switched-capacitor A/D Input Structures”, details  
various input architectures.  
The CS5510/11/12/13 ADCs are designed to oper-  
ate from a single +5 V supply or a variety dual-sup-  
ply configurations and are optimized to digitize  
bipolar signals in industrial applications.  
2.2 Voltage Reference Input  
The voltage between the VREF and V- pins of the  
converter determines the voltage reference for the  
converter. This voltage can be as low as 250 mV,  
or as great as (V+) - (V-). The VREF pin can be  
connected directly to the V+ pin. This will establish  
a voltage reference equal to (V+) - (V-) for the con-  
verter. The effective resolution of the part (noise-  
free bits for a single sample with no averaging) will  
vary with VREF. Figure 4 shows how the VREF  
voltage affects the noise-free resolution of the  
To achieve low cost, the CS5510/11/12/13 family  
of converters have no on-chip calibration features.  
The CS5510/11/12/13 offer very low offset drift,  
low gain drift, and excellent linearity.  
2.1 Analog Input  
The CS5510/11/12/13 provides a differential input  
span of approximately (0.80 0.08) times the dif-  
φ
Fine  
1
φ
Coarse  
1
AIN  
C
= 1  
2 F  
p
V
i
2 5 mV  
os  
=
f V  
C
os  
n
f = 32.768 kHz  
Figure 3. Input models for AIN+ and AIN- pins.  
10  
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