CS5510/11/12/13
SWITCHING CHARACTERISTICS - CS5510/12
(T = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; C = 50 pF)
A
L
Parameter
Symbol Min
Typ
Max
Unit
Master Clock Timing
Master Clock Frequency (CS5510)
Master Clock Frequency (CS5512)
Master Clock Duty Cycle
Rise Times
(Note 20) SCLK
(Note 20) SCLK
10
10
40
32.768 130
32.768 200
kHz
kHz
%
-
60
(Note 21)
CSB
t
rise
-
-
-
-
-
50
1.0
10
-
µs
µs
ns
SCLK
SDO
Fall Times
(Note 21)
CSB
t
fall
-
-
-
-
-
50
1.0
10
-
µs
µs
ns
SCLK
SDO
Serial Port Timing
Serial Clock Frequency (CS5510)
Serial Clock Frequency (CS5512)
SCLK High to Enter Sleep
SCLK Low to Exit Sleep
Serial Clock
(Note 22) SCLK
(Note 22) SCLK
10
10
32.768 130
32.768 200
kHz
kHz
µs
(Note 22)
t
200
10
-
-
2000
-
SLP
(Note 22) t
µs
WAKE
Pulse Width High
Pulse Width Low
t
t
2
2
-
-
60
60
µs
µs
1
2
SDO Read Timing
t
-
-
150
ns
CS to Data Valid
3
SCLK Falling to New Data Bit
t
t
-
-
-
-
150
150
ns
ns
4
CS Rising to SDO Hi-Z
5
t
200
-
-
ns
CS Falling to SCLK Rising
11
Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or
200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded
linearity specifications, as shown in Figures 14 and 15.
21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as
well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for t
or longer,
SLP
the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for t
or
WAKE
longer.
DS337F3
7
CIRRUS [ CIRRUS LOGIC ]
