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CS5513-BS 参数 Datasheet PDF下载

CS5513-BS图片预览
型号: CS5513-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 16位和20位, 8引脚Σ-Δ型ADC [16-bit and 20-bit, 8-pin Sigma-Delta ADC]
分类和应用:
文件页数/大小: 24 页 / 408 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5510/11/12/13  
ANALOG CHARACTERISTICS (Continued)  
Parameter  
Min  
Typ  
Max  
Unit  
Voltage Reference Input  
Range  
{(VREF) - (V-)}  
(Note 8) 0.250  
2.5  
7
(V+) - (V-)  
V
Input Capacitance  
CVF current  
-
-
-
-
pF  
nA  
6
Power Supplies  
Supply Voltages  
DC Power Supply Currents  
{(V+) - (V-)}  
4.75  
5
5.25  
V
(Note 9)  
I
I
CS5510  
CS5511  
CS5512  
CS5513  
CS5510  
CS5511  
CS5512  
CS5513  
-
-
-
-
-
-
-
-
275  
290  
360  
385  
275  
290  
360  
385  
360  
380  
470  
500  
360  
380  
470  
500  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
µA  
V+  
V-  
Power Consumption  
(Note 10)  
CS5510  
CS5511  
CS5512  
CS5513  
(Note 11)  
-
-
-
-
-
1.4  
1.5  
1.8  
1.9  
10  
1.9  
2.0  
2.5  
2.7  
-
mW  
mW  
mW  
mW  
µW  
Sleep  
Power Supply Rejection  
dc Positive Supply  
dc Negative Supply  
-
-
85  
85  
-
-
dB  
dB  
Notes: 8. VREF is referenced to V- and must be less than or equal to V+.  
9. Due to current through the CS pin, I and I may not always be the same value.  
V+  
V-  
10. All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)).  
11. CS must be inactive (logic high) during sleep to meet this power specification.  
DIGITAL CHARACTERISTICS  
(T = 25° C; V+ = 5 V ±5%; V- = 0 V) (See Notes 1 and 12.)  
A
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
High-Level Input Voltage:  
Low-Level Input Voltage:  
CS and SCLK  
V
CSLow  
V
V+ - 0.45  
-
-
V
IH  
(Note 13) CS  
SCLK  
-
-
-
-
V
V
V
V
L1  
L1  
IL  
Input Current:  
(Note 14) CS  
I
-
-
-
1.0  
-
mA  
V
CS  
High-Level Output Voltage:  
SDO, I  
= 5.0mA  
= 1.0mA  
V
(V+) - 0.6  
source  
OH  
Low-Level Output Voltage:  
(Note 14) SDO, I  
V
I
-
-
(CSLow) + 0.6  
V
sink  
OL  
Input Leakage Current  
3-State Leakage Current  
SCLK  
SCLK  
-
-
±0.015  
-
±10  
±10  
µA  
µA  
in  
I
OZ  
Notes: 12. All measurements performed under static conditions.  
13. V is 0.5 (V+ - V-) + 0.6 V + V-.  
L1  
14. The CS signal provides the sink current path for the SDO pin when CS is low. The external drive logic  
to CS, therefore, must be able to handle the logic-low current drive levels for all devices attached to  
SDO. The voltage specified for SDO is relative to CS . See Section 2.3.1, “Digital Logic Levels” and  
Low  
Figure 11 for more details.  
DS337F3  
5
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