CS5505/6/7/8
CS5505/6/7/8
AIN1. The BP/UP pin is not a latched input. The
BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is
offset by 8000H in the 16-bit CS5505/7 or
80000H in 20-bit CS5506/8 (see Understanding
Converter Calibration). BP/UP can be changed
after a conversion is started as long as it is stable
for 82 clock cycles of the conversion period
prior to DRDY falling. If one wishes to intermix
measurement of bipolar and unipolar signals on
various input channels, it is best to switch the
BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again. If
the converter is beginning a conversion starting
from the standby state, BP/UP can be changed at
the same time as A0 and A1.
terminated and a new conversion will be initi-
ated.
Voltage Reference
The CS5505/6/7/8 uses a differential voltage ref-
erence input. The positive input is VREF+ and
the negative input is VREF-. The voltage be-
tween VREF+ and VREF- can range from 1 volt
minimum to 3.6 volts maximum. The gain slope
will track changes in the reference without re-
calibration, accommodating ratiometric
applications.
The CS5505/6/7/8 include an on-chip voltage
reference which outputs 2.5 volts on the VRE-
FOUT pin. This voltage is referenced to the
VA+ pin and will track changes relative to VA+.
The VREFOUT output requires a 0.1 µF capaci-
tor connected between VREFOUT and VA+ for
stability. When using the internal reference, the
VREFOUT signal should be connected to the
VREF- input and the VREF+ pin should be con-
nected to the VA+ supply. The internal voltage
reference is capable of sourcing 3 µA maximum
and sinking 50 µA maximum. If a more precise
reference voltage is required, an external voltage
reference should be used. If an external voltage
reference is used, the VREFOUT pin of the in-
ternal reference should be connected directly to
VA-. It cannot be left open unless the 0.1 µF ca-
pacitor is in place for stability.
The digital filter in the CS5505/6/7/8 has a Fi-
nite Impulse Response and is designed to settle
to full accuracy in one conversion time. There-
fore, the multiplexer can be changed at the
conversion rate.
If CONV is left high, the CS5505/6/7/8 will per-
form continuous conversions on one channel.
The conversion time will be 1622 clock cycles.
If conversion is initiated from the standby state,
there may be up to two XIN clock cycles of un-
certainty as to when conversion actually begins.
This is because the internal logic operates at one
half the external clock rate and the exact phase
of the internal clock may be 180° out of phase
relative to the XIN clock. When a new conver-
sion is initiated from the standby state, it will
take up to two XIN clock cycles to begin. Actual
conversion will use 1624 clock cycles before
DRDY goes low to indicate that the serial port
has been updated. See the Serial Interface Logic
section of the data sheet for information on read-
ing data from the serial port.
CS5505/6/7/8
VA+
+VA
LT1019,
2.5V
VREF+
REF43
or
LM368
VREF-
VREFOUT
VA-
-VA
In the event the A/D conversion command
(CONV going positive) is issued during the con-
version state, the current conversion will be
Figure 5. External Reference Connections
DDSS599FF45
1155
CIRRUS [ CIRRUS LOGIC ]
