CS5471
centage of full scale. Table 1 below illustrates the
ideal relationship between the differential voltage
presented any one of the input channels and the
corresponding output code. Note that for the cur-
rent channels, the state of the GAIN input pin is as-
sumed to driven low, such that the PGA gain on the
current channels is 1x. If the PGA gain of the cur-
rent channels is set to 20x, then a +40 mV differen-
tial voltage presented across the “IIN+” and “IIN-”
pins will cause a (nominal) output code of 32767.
3
–256
1 – z
---------------------
–1
H(z) =
1 – z
If the OWRS pin is set to logic high, then the trans-
fer function is
Input Voltage
(mV0-pk)
Output Code Output Code
3
–128
1 – z
(hexadecimal)
(decimal)
---------------------
–1
H(z) =
+800
7FFF
32767
1 – z
0.0122 to 0.0366
-0.0122 to 0.0122
-0.0122 to -0.0366
-800
0001
1
0
0000
The above filter samples the modulator bit stream
at XIN/8 Hz and decimates to XIN/1024 Hz.
FFFF
-1
8000
-32768
2.4
Serial Interface
Table 1. Nominal Relationship for Differential Input
Voltage vs. Output Code, for all channels. (Assume PGA
gain is set to 1x.)
The CS5471 communicates with a target device via
a master serial data output port. Output data is pro-
vided on the SDO output synchronous with the
SCLK output.
2.3
High Rate Digital Filters
If the OWRS pin is set to logic low, the high-rate
A third output, FSO, is a framing signal used to sig-
nal the start of output data. These three outputs will
be driven as long as the SE (serial enable) input is
held high. Otherwise, these outputs will be high im-
pedance.
3
filters are implemented as fixed sinc filters with
the following transfer function:
This filter samples the modulator bit stream at
XIN/8 Hz and decimates to XIN/2048 Hz.
SCLK
FSO
Each data segment
is 16 bits long.
SDO
Channel 1 (V)
64 0-value bits
Channel 1 (I)
Figure 3. Serial Port Data Transfer
8
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