CS5471
SWITCHING CHARACTERISTICS (TA = -40 °C to +85 °C; VA+, VD+ = 3.0 V 10%; VA- = -2 V
10%; DGND = AGND = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF))
Parameter
Symbol
Min
3
Typ
4.000
-
Max
5
Unit
MHz
%
Master Clock Frequency
Master Clock Duty Cycle
Rise Times
(Note 12)
XIN
-
40
60
Any Digital Input (Note 13)
Any Digital Output
trise
-
-
-
50
1.0
-
µs
ns
Fall Times
Any Digital Input (Note 13)
Any Digital Output
tfall
-
-
-
50
1.0
-
µs
ns
Serial Port Timing
Serial Clock Frequency
(Note 12)
OWRS = “0”
OWRS = “1”
SCLK
SCLK
-
-
500
1000
-
-
kHz
kHz
Serial Clock
Pulse Width High (Note 12)
Pulse Width Low (Note 12)
t1
t2
-
-
0.5
0.5
-
-
SCLK
SCLK
SCLK falling to New Data Bit
FSO Falling to SCLK Rising Delay
FSO Pulse Width
t3
t4
t5
t6
t7
-
-
-
-
-
-
0.5
1
50
-
ns
SCLK
SCLK
ns
(Note 12)
(Note 12)
-
SE Rising to Output Enabled
SE Falling to Output in Tri-state
-
50
50
-
ns
Notes: 12. Device parameters are specified with a 4.000 MHz clock, OWRS = 1.
13. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
MSB(V1) MSB(V1) - 1
LSB(I2)
SDO
SCLK
FSO
t3
t1
t2
t 4
t 5
t 6
SE
t 6
Figure 1. Serial Port Timing
6
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