CS5471
3. PIN DESCRIPTION
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Serial Clock Output
Serial Data Output
Frame Sync
Serial Port Enable
Current Input Gain
Analog Ground
SCLK
SDO
FSO
VD+
Digital Supply
Digital Ground
Charge Pump Drive
Master Clock
Reset
Output Word Rate Select
Differential Voltage Input 1
Differential Voltage Input 1
Differential Current Input 1
Differential Current Input 1
DGND
CPD
XIN
RESET
OWRS
VIN+
VIN-
SE
GAIN
AGND
VREFIN
Reference Input
Reference Output VREFOUT
Positive Analog Supply
Negative Analog Supply
VA+
VA-
IIN+
IIN-
Clock Generator
XIN - Master Clock Input
Control Pins and Serial Data I/O
SE - Serial Port Enable.
When SE is low, the output pins of the serial port are 3-stated.
SDO - Serial Port Output.
Data will be at a rate determined by SCLK.
FSO - Frame Signal Output.
Framing signal output for data transfer from SDO pin.
SCLK - Serial Clock Output.
A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined
by XIN frequency and state of OWRS input pin.
RESET - Reset.
When reset is taken low, all internal registers are set to their default states.
GAIN - Input Gain Control.
Sets input gain for current channel. A logic high sets internal gain to 1, a logic low level sets the gain to
20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor
to DGND).
OWRS - Output Word Rate Select.
When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to
logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will
default to logic low level (through internal 200K resistor to DGND).
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CIRRUS [ CIRRUS LOGIC ]
