CS5463
V
*
*
VDCoff
gn
X
Digital Filter
PMF
HHPPFF
+
2nd Order
∆Σ
Modulator
*
V
IIR
DELAY
REG
+
DELAY
REG
3
VOLTAGE
x10
X
SINC
Σ
*
VQ
+
*
Q
X
X
Σ
+
6
*
ε
X
∫
*
XVDEL XIDEL VHPF IHPF
IIR
4
SYSGain
...
PC6 PC5 PC4 PC3 PC2 PC1 PC0
Configuration Register *
2322
3 2 1 0
8
7
6
5
2π
Operational Modes Register *
*
X
P
4th Order
∆Σ
Modulator
IIR
+
DELAY
REG
DELAY
REG
3
SINC
X
HPF
PMF
X
Σ
CURRENT PGA
*
I
+
*
DENOTES REGISTER NAME.
I
*
Digital Filter
IDCoff
*
gn
Figure 3. Data Measurement Flow Diagram.
4. THEORY OF OPERATION
The CS5463 is a dual-channel analog-to-digital convert-
er (ADC) followed by a computation engine that per-
forms power calculations and energy-to-pulse
conversion. The data flow for the voltage and current
channel measurement and the power calculation algo-
rithms are depicted in Figure 3 and 4, respectively.
from the calculated V
ent power.
and I
as well as the appar-
RMS
RMS
When the optional HPF in either channel is disabled an
all-pass filter (APF) is implemented. The APF has an
amplitude response that is flat within the channel band-
width and is used for matching phase in systems where
one HPF is engaged.
The analog inputs are structured with two dedicated
channels, voltage and current, then optimized to simpli-
fy interfacing to various sensing elements.
4.2 Voltage and Current Measurements
The digital filter output word is then subject to a DC off-
set adjustment and a gain calibration (See Section 7.
System Calibration on page 36). The calibrated mea-
surement is available by reading the instantaneous volt-
age and current registers
The voltage-sensing element introduces a voltage
waveform on the voltage channel input VIN± and is sub-
ject to a gain of 10x. A second-order delta-sigma modu-
lator samples the amplified signal for digitization.
Simultaneously, the current sensing element introduces
a voltage waveform on the current channel input IIN±
and is subject to the two selectable gains of the pro-
grammable gain amplifier (PGA). The amplified signal is
sampled by a fourth-order delta-sigma modulator for
digitization. Both converters sample at a rate of
MCLK/8, the over-sampling provides a wide dynamic
range and simplified anti-alias filter design.
The Root Mean Square (RMS in Figure 4) calculations
are performed on N instantaneous voltage and current
samples, Vn and In respectively (where N is the cycle
count), using the formula:
N – 1
I
∑
n
I
=
RMS
n = 0
--------------------
N
4.1 Digital Filters
The decimating digital filters on both channels are Sinc
3
and likewise for VRMS, using Vn. IRMS and VRMS are ac-
cessible by register reads, which are updated once ev-
ery cycle count (referred to as a computational cycle).
filters followed by 4th-order IIR filters. The single-bit
data is passed to the low-pass decimation filter and out-
put at a fixed word rate. The output word is passed to an
optional IIR filter to compensate for the magnitude
roll-off of the low-pass filtering operation.
4.3 Power Measurements
The instantaneous voltage and current samples are
multiplied to obtain the instantaneous power (see Fig-
ure 3). The product is then averaged over N conver-
sions to compute active power and is used to drive
energy pulse outputs E1. Energy output E2 is select-
able, providing an energy sign or a pulse output that is
proportional to the apparent power. Energy output E3
An optional digital high-pass filter (HPF in Figure 3) re-
moves any DC component from the selected signal
path. By removing the DC component from the voltage
and/or the current channel, any DC content will also be
removed from the calculated active power as well. With
both HPFs enabled the DC component will be removed
14
DS678PP1
CIRRUS [ CIRRUS LOGIC ]
