CS5463
5. FUNCTIONAL DESCRIPTION
5.1 Analog Inputs
The CS5463 is equipped with two fully differential input
channels. The inputs VIN and IIN are designated as
the voltage and current channel inputs, respectively.
The full-scale differential input voltage for the current
The Current Gain Register also allows for an additional
programmable gain of up to 4x. If an additional gain is
applied to the voltage and/or current channel, the maxi-
mum input range should be adjusted accordingly.
5.2 IIR Filters
and voltage channel is 250 mV .
P
The current and voltage channel are equipped with a
4th-order IIR filter, that is used to compensate for the
magnitude roll-off of the low-pass decimation filter. Op-
erational Mode Register bit IIR engages the IIR filters in
both the voltage and current channel.
5.1.1 Voltage Channel
The output of the line voltage resistive divider or trans-
former is connected to the VIN+ and VIN- input pins of
the CS5463. The voltage channel is equipped with a
10x fixed gain amplifier. The full-scale signal level that
can be applied to the voltage channel is 250 mV. If the
input signal is a sine wave the maximum RMS voltage
at a gain 10x is:
5.3 High-pass Filters
By removing the offset from either channel, no error
component will be generated at DC when computing the
active power. By removing the offset from both chan-
nels, no error component will be generated at DC when
250mV
P
--------------------
≅ 176.78mV
RMS
computing V
, I
and apparent power. Operation-
2
RMS RMS
al Mode Register bits VHPF and IHPF activate the HPF
in the voltage and current channel respectively. When a
high-pass filter is engaged in only one channel, an
all-pass filter (APF) is applied to the other channel.
which is approximately 70.7% of maximum peak volt-
age. The voltage channel is also equipped with a Volt-
age Gain Register, allowing for an additional
programmable gain of up to 4x.
5.4 Performing Measurements
The CS5463 performs measurements of instantaneous
5.1.2 Current Channel
The output of the current sense resistor or transformer
is connected to the IIN+ and IIN- input pins of the
CS5463. To accommodate different current sensing el-
ements the current channel incorporates a Programma-
ble Gain Amplifier (PGA) with two programmable input
gains. Configuration Register bit Igain (see Table 1) de-
fines the two gain selections and corresponding maxi-
mum input signal level.
voltage (V ) and current (I ), and calculates instanta-
n
n
neous power (P ) at an Output Word Rate (OWR) of
n
(MCLK ⁄ K)
----------------------------
OWR =
1024
where K is the clock divider selected in the Configura-
tion Register.
The RMS voltage (V
), RMS current (I
) and ac-
RMS
RMS
Igain
Maximum Input Range
tive power (P
) are computed, using N instanta-
active
neous samples of V , I and P respectively, where N is
the value in the Cycle Count Register and is referred to
as a “computation cycle”. The apparent power (S) is the
0
1
±250 mV
±50 mV
10x
50x
n
n
n
Table 1. Current Channel PGA Setting
product of V
and I
. A computation cycle is de-
RMS
RMS
rived from the master clock (MCLK), with frequency:
For example, if Igain=0, the current channel’s PGA gain
is set to 10x. If the input signals are pure sinusoids with
zero phase shift, the maximum peak differential signal
OWR
---------------
Computation Cycle =
N
on the current or voltage channel is 250 mV . The in-
P
Under default conditions and with K = 1, N = 4000, and
MCLK = 4.096 MHz – the OWR = 4000 Hz and the
Computation Cycle = 1 Hz.
put signal levels are approximately 70.7% of maximum
peak voltage producing a full-scale energy pulse regis-
tration equal to 50% of absolute maximum energy pulse
registration. This will be discussed further in See Sec-
tion 5.5 Energy Pulse Output on page 17.
All measurements are available as a percentage of full
scale. The format for signed registers is a two’s comple-
ment, normalized value between -1 and +1. The format
16
DS678PP1
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