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CS5460A-BS 参数 Datasheet PDF下载

CS5460A-BS图片预览
型号: CS5460A-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 单相双向功率/电能IC [Single Phase Bi-Directional Power/Energy IC]
分类和应用:
文件页数/大小: 54 页 / 879 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5460A  
6. PIN DESCRIPTION  
Crystal Out  
XOUT  
CPUCLK  
VD+  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
XIN  
Crystal In  
CPU Clock Output  
Positive Digital Supply  
Digital Ground  
SDI  
Serial Data Input  
2
EDIR  
EOUT  
INT  
Energy Direction Indicator  
Energy Output  
3
DGND  
SCLK  
SDO  
4
Serial Clock Input  
Serial Data Output  
Chip Select  
Interrupt  
5
RESET  
NC  
Reset  
6
CS  
No Connect  
7
Mode Select  
MODE  
VIN+  
PFMON  
IIN+  
IIN-  
Power Fail Monitor  
Differential Current Input  
Differential Current Input  
Positive Analog Supply  
Analog Ground  
8
Differential Voltage Input  
Differential Voltage Input  
9
VIN-  
10  
11  
12  
Voltage Reference Output VREFOUT  
Voltage Reference Input VREFIN  
VA+  
VA-  
Clock Generator  
1,24  
2
XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a  
crystal to provide the system clock for the device. Alternatively, an external (CMOS  
compatible clock) can be supplied into XIN pin to provide the system clock for the device.  
Crystal Out  
Crystal In  
CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.  
CPU Clock Output  
Control Pins and Serial Data I/O  
5
SCLK - A clock signal on this pin determines the input and output rate of the data for the  
SDI and SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time  
signals. The SCLK pin will recognize clocks only when CS is low.  
Serial Clock Input  
6
7
8
SDO - SDO is the output pin of the serial data port. Its output will be in a high impedance  
state when CS is high.  
Serial Data Output  
Chip Select  
CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO  
pin to a high impedance state. CS should be changed when SCLK is low.  
MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the  
aid of an external serial EEPROM to receive commands and settings. When at logic low,  
the CS5460A assumes normal “host mode” operation. This pin is pulled down to logic  
low if left unconnected, by an internal pull-down resistor to DGND.  
Mode Select  
20  
21  
22  
INT - When INT goes low it signals that an enabled event has occurred. INT is cleared  
(logic 1) by writing the appropriate command to the CS5460A.  
Interrupt  
EOUT - The energy output pin output a fixed-width pulse rate output with a rate (pro-  
grammable) proportional to real (billable) energy.  
Energy Output  
Energy Direction  
Indicator  
EDIR - The energy direction indicator indicates if the measured energy is negative.  
SDI - the input pin of the serial data port. Data will be input at a rate determined by SCLK.  
23  
Serial Data Input  
Measurement and Reference Input  
9,10  
VIN+, VIN- - Differential analog input pins for voltage channel.  
Differential  
Voltage Inputs  
51  
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