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CS5460A-BS 参数 Datasheet PDF下载

CS5460A-BS图片预览
型号: CS5460A-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 单相双向功率/电能IC [Single Phase Bi-Directional Power/Energy IC]
分类和应用:
文件页数/大小: 54 页 / 879 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5460A  
CRDY  
Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate,  
which is usually 4 kHz.  
EDIR  
Set whenever the EOUT bit asserted (see below) if the accumulated energy is negative.  
EOUT  
Indicates that enough positive/negative energy has been reached within the internal EOUT En-  
ergy Accumulation Register (not accessible to user) to mandate the generation of one or more  
pulses on the EOUT pin (if enabled, see Configuration Register). The energy flow may indicate  
negative energy or positive energy. (The sign is determined by the EDIR bit, described above).  
This EOUT bit is cleared automatically when the energy rate drops below the level that produc-  
es a 4 kHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This  
status bit is set with a maximum frequency of 4 kHz (when MCLK/K is 4.096 MHz). When  
MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate by a factor of  
4.096 MHz / (MCLK/K) to get the actual pulse-rate.  
DRDY  
Data Ready. When running in ’single computation cycle’ or ’continuous computation cycles’  
data acquisition modes, this bit will indicate the end of computation cycles. When running cali-  
brations, this bit indicates that the calibration sequence has completed, and the results have  
been stored in the offset or gain registers.  
5.12 Control Register  
Address: 28  
23  
22  
21  
20  
19  
18  
17  
16  
Res  
Res  
Res  
Res  
Res  
Res  
Res  
Res  
15  
14  
13  
12  
11  
10  
9
8
Res  
Res  
Res  
Res  
Res  
Res  
Res  
STOP  
7
6
5
4
3
2
1
0
Res  
MECH  
Res  
INTL  
SYNC  
NOCPU  
NOOSC  
STEP  
Default** = 0x000000  
STOP  
Res  
1 = used to terminate the new EEBOOT sequence.  
Reserved. These bits must be set to zero.  
MECH  
INTL  
1 = widens EOUT and EDIR pulses for mechanical counters.  
1 = converts the INT output to open drain configuration.  
SYNC  
NOCPU  
NOOSC  
STEP  
1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command.  
1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption.  
1 = saves power by disabling the crystal oscillator for external drive.  
1 = enables stepper-motor signals on the EOUT/EDIR pins.  
50  
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