CS5460A
*
V
*
*
V
VDCoff
VACoff
*
gn
x
DELAY
REG
DELAY
REG
∆Σ
2
2
N
x
-
V
*
RMS
+
VOLTAGE
FIR
HPF
APF
SINC
N
÷
SINC
TBC *
x
*
P
off
Configuration Register *
PC[6:0] Bits
N
÷
4096
x
E *
E
+
Σ
*
E to F
out
P
E
dir
PULSE-RATE*
4
CURRENT
∆Σ
2
N
x
x
SINC
+
-
I
*
FIR
HPF
APF
N
÷
SINC
RMS
*
I
I
*
*
IDCoff
IACoff
*
gn
* DENOTES REGISTER NAME
Figure 3. Data Flow.
Figure 3) will be enabled on the other channel; in
order to preserve the relative phase relationship
between the voltage-sense and current-sense in-
put signals. For example, if the HPF is engaged for
the voltage channel, but not the current channel,
then the APF will be engaged in the current channel,
to nullify the additional phase delay introduced by
the high-pass filter in the current channel.
instantaneous voltage/current data samples are
multiplied together (one multiplication for each pair
of voltage/current samples) to form instantaneous
(real) power samples. After each A/D conversion
cycle, the new instantaneous power sample is
stored in the Instantaneous Power Register.
The instantaneous power samples are then
grouped into sets of N samples (where N = value in
Cycle Count Register). The cumulative sum of
each successive set of N instantaneous power is
used to compute the result stored in the Energy
Register, which will be proportional to the amount
of real energy registered by the device during the
most recent N A/D conversion cycles. Note from
Figure 3 that the bits in this running energy sum
are right-shifted 12 times (divided by 4096) to
avoid overflow in the Energy Register. RMS calcu-
lations are also performed on the data using the
last N instantaneous voltage/current samples, and
these results can be read from the RMS Voltage
Register and the RMS Current Register.
2.1.5 Overall Filter Response
When the CS5460A is driven with a 4.096 MHz
clock (K = 1), the composite magnitude response
(over frequency) of the voltage channel’s input fil-
ter network is shown in Figure 4, while the com-
posite magnitude response of the current
channel’s input filter network is given in Figure 5.
Note that the composite filter response of both
channels scales with MCLK frequency and K.
2.1.6 Gain and DC Offset Adjustment
After filtering, the instantaneous voltage and cur-
rent digital codes are subjected to offset/gain ad-
justments, based on the values in the DC offset
registers (additive) and the gain registers (multipli-
cative). These registers are used for calibration of
the device (see Section 3.8, Calibration). After off-
set and gain, the 24-bit instantaneous data sample
values are stored in the Instantaneous Voltage and
Current Registers.
2.2 Performing Measurements
To summarize Section 2.1, the CS5460A performs
measurements of instantaneous current and in-
stantaneous voltage, and from this, performs com-
putations of the corresponding instantaneous
power, as well as periodic calculations of real en-
ergy, RMS current, and RMS voltage. These mea-
surement/calculation results are available in the
form of 24-bit signed and unsigned words. The
scaling of all output words is normalized to unity
2.1.7 Real Energy and RMS Computations
The digital instantaneous voltage and current data
is then processed further. Referring to Figure 3, the
13
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