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CS5460A-BS 参数 Datasheet PDF下载

CS5460A-BS图片预览
型号: CS5460A-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 单相双向功率/电能IC [Single Phase Bi-Directional Power/Energy IC]
分类和应用:
文件页数/大小: 54 页 / 879 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5460A  
2. GENERAL DESCRIPTION  
2.1.1 ∆Σ Modulators  
The CS5460A is a CMOS monolithic power mea-  
surement device with a real power/energy compu-  
tation engine. The CS5460A combines two  
programmable gain amplifiers, two ∆Σ modulators,  
two high rate filters, system calibration, and  
rms/power calculation functions to provide instan-  
taneous voltage/current/power data samples as  
well as periodic computation results for real (bill-  
The analog waveforms at the voltage/current chan-  
nel inputs are subject to the gains of the input  
PGAs (not shown in Figure 3). These waveforms  
are then sampled by the delta-sigma modulators at  
a rate of (MCLK/K)/8 Sps.  
2.1.2 High-Rate Digital Low-Pass Filters  
The data is then low-pass filtered, to remove  
high-frequency noise from the modulator output.  
Referring to Figure 3, the high rate filter on the volt-  
able) energy, V  
, and I  
. In order to accom-  
RMS  
RMS  
modate lower cost metering applications, the  
CS5460A can also generate pulse-train signals on  
certain output pins, for which the number of pulses  
emitted on the pins is proportional to the quantity of  
real (billable) energy registered by the device.  
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age channel is implemented as a fixed Sinc filter.  
4
The current channel uses a Sinc filter, which al-  
lows the current channel to make accurate mea-  
surements over a wider span of the total input  
range, in comparison to the accuracy range of the  
voltage channel. (This subject is discussed more in  
Section 2.2.1)  
The CS5460A is optimized for power measure-  
ment applications and is designed to interface to a  
shunt or current transformer to measure current,  
and to a resistive divider or potential transformer to  
measure voltage. To accommodate various input  
voltage levels, the current channel includes a pro-  
grammable gain amplifier (PGA) which provides  
two full-scale input levels, while the voltage chan-  
nel’s PGA provides a single input voltage range.  
With a single +5 V supply on VA+/-, both of the  
CS5460A’s input channels can accomodate com-  
mon mode + signal levels between -0.25 V and  
VA+.  
Also note from Figure 3 that the digital data on the  
voltage channel is subjected to a variable time-de-  
lay filter. The amount of delay depends on the val-  
ue of the seven phase compensation bits (see  
Phase Compensation). Note that when the phase  
compensation bits PC[6:0] are set to their default  
setting of “0000000” (and if MCLK/K = 4.096 MHz)  
then the nominal time delay that is imposed on the  
original analog voltage input signal, with respect to  
the original analog current input signal, is ~1.0 µs.  
This translates into a delay of ~0.0216 degrees at  
60 Hz.  
The CS5460A includes two high-rate digital filters  
(one per channel), which decimate/integrate the  
output from the 2 ∆Σ modulators. The filters yield  
24-bit output data at a (MCLK/K)/1024 output word  
rate (OWR). The OWR can be thought of as the ef-  
fective sample frequency of the voltage channel and  
the current channel.  
2.1.3 Digital Compensation Filters  
The data from both channels is then passed  
through two FIR compensation filters, whose pur-  
pose is to compensate for the magnitude roll-off of  
the low-pass filtering operation (mentioned earli-  
er).  
To facilitate communication to a microcontroller,  
the CS5460A includes a simple three-wire serial  
interface which is SPI™ and Microwire™ compati-  
ble. The serial port has a Schmitt Trigger input on  
its SCLK (serial clock) and RESET pins to allow for  
slow rise time signals.  
2.1.4 Digital High-Pass Filters  
Both channels provide an optional high-pass filter  
(denoted as “HPF” in Figure 3) which can be en-  
gaged into the signal path, to remove the DC con-  
tent from the current/voltage signal before the  
RMS/energy calculations are made. These filters  
are activated by enabling certain bits in the Config-  
uration Register.  
2.1 Theory of Operation  
A computational flow diagram for the two data  
paths is shown in Fig. 3. The reader should refer to  
this diagram while reading the following data pro-  
If e high-pass filter is engaged in only one of the  
two channels, then the all-pass filter (see “APF” in  
cessing  
description,  
which  
is  
covered  
block-by-block.  
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