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CS5460A-BS 参数 Datasheet PDF下载

CS5460A-BS图片预览
型号: CS5460A-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 单相双向功率/电能IC [Single Phase Bi-Directional Power/Energy IC]
分类和应用:
文件页数/大小: 54 页 / 879 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5460A  
full-scale. Note that the 24-bit signed output words  
are expressed in two’s complement format. The  
24-bit data words in the CS5460A output registers  
represent values between 0 and 1 (for unsigned  
output registers) or between -1 and +1 (for signed  
output registers). A register value of 1 represents  
the maximum possible value. Note that a value of  
1.0 is never actually obtained in the registers of the  
CS5460A. As an illustration, in any of the signed  
output registers, the maximum register value is  
[(2^23 - 1) / (2^23)] = 0.999999880791. After each  
A/D conversion, the CRDY bit will be asserted in  
the Status Register, and the INT pin will also be-  
come active if the CRDY bit is unmasked (in the  
Mask Register). The assertion of the CRDY bit in-  
dicates that new instantaneous 24-bit voltage and  
current samples have been collected, and these  
two samples have also been multiplied together to  
provide a corresponding instantaneous 24-bit pow-  
er sample.  
Output Code Output Code  
Input Voltage (DC) (hexidecimal)  
(decimal)  
7FFFFF  
000001  
000000  
FFFFFF  
800000  
8388607  
+250 mV  
1
14.9 nV to 44.7 nV  
-14.9 nV to 14.9 nV  
-44.7 nV to -14.9 nV  
-250 mV  
0
-1  
-8388608  
Table 1. Differential Input Voltage vs. Output Code  
The V  
, I  
, and energy calculations are up-  
RMS RMS  
dated every N conversions (which is known as 1  
computation cycle”), where N is the value in the  
Cycle Count Register. At the end of each computa-  
tion cycle, the DRDY bit in the Mask Register will  
be set, and the INT pin will become active if the  
DRDY bit is unmasked.  
DRDY is set only after each computation cycle has  
completed, whereas the CRDY bit is asserted after  
each individual A/D conversion. Bits asserted by  
the CS5460A must be cleared before being assert-  
ed again. If the Cycle Count Register value (N) is  
set to 1, all output calculations are instantaneous,  
and DRDY will indicate when instantaneous calcu-  
lations are finished, just like the CRDY bit. For the  
RMS results to be valid, the Cycle-Count Register  
must be set to a value greater than 10.  
Table 1 conveys the typical relationship between  
the differential input voltage (across the “+” and “-”  
input pins of the voltage channel input) and the cor-  
responding output code in the Instantaneous Volt-  
age Register. Note that this table is applicable for  
the current channel if the current channel’s PGA  
gain is set for the “10x” gain mode.  
The computation cycle frequency is derived from  
the master clock, and has  
a
value of  
(MCLK/K)/(1024*N). Under default conditions, with  
0.5  
0.0  
0.5  
0
-0.5  
-1.0  
-1.5  
-2.0  
-2.5  
-0.5  
-1  
-1.5  
-2  
-2.5  
0
200 400  
600 800 1000 1200 1400 1600 1800 2000  
0
200 400  
600 800 1000 1200 1400 1600 1800 2000  
Frequency (Hertz)  
Frequency (Hertz)  
Figure 5. Current Input Filter Characteristics  
Figure 4. Voltage Input Filter Characteristics  
14