CS5101A CS5102A
As with any high-precision A/D converter, the
CS5101A and CS5102A require careful attention
to grounding and layout arrangements. However,
no unique layout issues must be addressed to
properly apply the devices. The CDB5101A
evaluation board is available for the CS5101A,
and the CDB5102A evaluation board is available
for the CS5102A. The availability of these boards
avoids the need to design, build, and debug a
high-precision PC board to initially characterize
the part. Each board comes with a socketed
CS5101A or CS5102A, and can be reconfigured
to simulate any combination of sampling, calibra-
tion, master clock, and analog input range
conditions.
They can be analyzed as step functions superim-
posed on the input signal. Since bits (and their
errors) switch in and out throughout the transfer
curve, their effect is signal dependent. That is,
harmonic and intermodulation distortion, as well
as noise, can vary with different input conditions.
Differential nonlinearities in successive-approxi-
mation ADC’s also arise due to dynamic errors in
the comparator. Such errors can dominate if the
converter’s throughput/sampling rate is too high.
The comparator will not be allowed sufficient
time to settle during each bit decision in the suc-
cessive-approximation algorithm. The worst-case
codes for dynamic errors are the major transitions
(1/2 FS; 1/4, 3/4 FS; etc.). Since DNL effects are
most critical with low-level signals, the codes
around mid-scale (1/2 FS) are most important.
Yet those codes are worst-case for dynamic DNL
errors!
CS5101A AND CS5102A PERFORMANCE
Differential Nonlinearity
The self-calibration scheme utilized in the
CS5101A and CS5102A features a calibration
resolution of 1/4 LSB, or 18-bits. This ideally
yields DNL of ±1/4 LSB, with code widths rang-
ing from 3/4 to 5/4 LSB’s.
With all linearity calibration performed on-chip
to 18-bits, the CS5101A and CS5102A maintain
accurate bit weights. DNL errors are dominated
by residual calibration errors of ±1/4 LSB rather
than dynamic errors in the comparator. Further-
more, all DNL effects on S/(N+D) are buried by
white broadband noise. (See Figures 17 and 19).
Traditional laser trimmed ADC’s have significant
differential nonlinearities. Appearing as wide and
narrow codes, DNL often causes entire sections
of the transfer function to be missing. Although
their affect is minor on S/(N+D) with high ampli-
tude signals, DNL errors dominate performance
with low-level signals. For instance, a signal 80
dB below full-scale will slew past only 6 or 7
codes. Half of those codes could be missing with
a conventional 16-bit ADC which achieves only
14-bit DNL.
Figure 11 illustrates the DNL histogram plot of a
typical CS5101A at 25°C. Figure 12 illustrates
the DNL of the CS5101A at 138°C ambient after
calibration at 25°C ambient. Figures 13 and 14
illustrate the DNL of the CS5102A at 25°C and
138°C ambient, respectively. A histogram test is a
statistical method of deriving an A/D converter’s
differential nonlinearity. A ramp is input to the
A/D and a large number of samples are taken to
insure a high confidence level in the test’s result.
The number of occurrences for each code is
monitored and stored. A perfect A/D converter
would have all codes of equal size and therefore
equal numbers of occurrences. In the histogram
test a code with the average number of occur-
rences will be considered ideal (DNL = 0). A
The most common source of DNL errors in con-
ventional ADC’s is bit weight errors. These can
arise due to accuracy limitations in factory trim
stations, thermal or physical stresses after calibra-
tion, and/or drifts due to aging or temperature
variations in the field. Bit-weight errors have a
drastic effect on a converter’s ac performance.
DS45F2
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