CS5101A CS5102A
tegrity. Whenever the array is switched during
conversion, the buffer is used to coarse-charge
the array thereby providing the bulk of the neces-
sary charge. The appropriate array capacitors are
then switched to the unbuffered VREF pin to avoid
any errors due to offsets and/or noise in the buffer.
CS5101A
OR
+5V
VD+
CS5102A
R
____
RST
1N4148
The external reference circuitry need only pro-
vide the residual charge required to fully charge
the array after coarse-charging from the buffer.
This creates an ac current load as the CS5101A
and CS5102A sequence through conversions. The
reference circuitry must have a low enough out-
put impedance to drive the requisite current
without changing its output voltage significantly.
As the analog input signal varies, the switching
sequence of the internal capacitor array changes.
The current load on the external reference cir-
cuitry thus varies in response with the analog
input. Therefore, the external reference must not
exhibit significant peaking in its output imped-
ance characteristic at signal frequencies or their
harmonics.
C
Figure 8. Power-up Reset Circuit
be tied to the same source, as CH1/2 is reconfig-
ured as an output.)
ANALOG CIRCUIT CONNECTIONS
Most popular successive approximation A/D con-
verters generate dynamic loads at their analog
connections. The CS5101A and CS5102A inter-
nally buffer all analog inputs (AIN1, AIN2,
VREF, and AGND) to ease the demands placed
on external circuitry. However, accurate system
operation still requires careful attention to details
at the design stage regarding source impedances
as well as grounding and decoupling schemes.
A large capacitor connected between VREF and
AGND can provide sufficiently low output im-
pedance at the high end of the frequency
spectrum, while almost all precision references
exhibit extremely low output impedance at dc.
The presence of large capacitors on the output of
some voltage references, however, may cause
peaking in the output impedance at intermediate
frequencies. Care should be exercised to ensure
that significant peaking does not exist or that
some form of compensation is provided to elimi-
nate the effect.
Reference Considerations
An application note titled "Voltage References for
the CS501X Series of A/D Converters" is avail-
able for the CS5101A and CS5102A. In addition to
working through a reference circuit design example,
it offers several built-and-tested reference circuits.
During conversion, each capacitor of the cali-
brated capacitor array is switched between VREF
and AGND in a manner determined by the suc-
cessive-approximation algorithm. The charging
and discharging of the array results in a current
load at the reference. The CS5101A and
CS5102A each include an internal buffer ampli-
fier to minimize the external reference circuit’s
drive requirement and preserve the reference’s in-
The magnitude of the current load on the external
reference circuitry will scale to the master clock
frequency. At the full-rated 9.216 MHz clock
(CS5101A), the reference must supply a maxi-
mum load current of 20 µA peak-to-peak (2 µA
typical). An output impedance of 2 Ω will there-
fore yield a maximum error of 40 µV. At the
full-rated 2.0 MHz clock (CS5102A), the refer-
20
DS45F2
CIRRUS [ CIRRUS LOGIC ]
