CS5101A CS5102A
10
+5VA
+
+
4.7
µF
0.1
µF
0.1
µF
1 µF
25
VA+
26
TST VD+
XOUT
7
4
C1
XTAL
VD+
10 M
3
CLKIN
C2 = C1
18
OUTMOD
SCKMOD
27
17
16
Mode Control
2
28
5
BP/UP
CODE
RST
SLEEP
STBY
EXT
CLOCK
CS5101A
Control
Logic
XTAL & C1 Table
OR
13
10
12
CH1/2
CRS/FIN
HOLD
XTAL
C1, C2
10 pF
20
22
CS5102A
VREF
AGND
CS5101A
FRN
Voltage Reference
8.0 MHz
PDT, RBT,
SSC
8.192 MHz 10 pF
8
9
TRK1
TRK2
CS5102A
FRN
1.6 MHz
30 pF
50
*
19
AIN1
AIN2
11
1.6 MHz
NPO
SSH/SDL
PDT, RBT,
SSC
Analog
Sources
1 nF
50
or
30 pF
2.0 MHz
24
*
14
15
SCLK
SDATA
DGND
NPO
Data
1 nF
Interface
* For best dynamic
S/(N+D) performance.
6
21
REFBUF
VA-
23
VD-
1
Unused Logic inputs should
be tied to VD+ or DGND.
0.1 µF
10
-5VA
4.7
µF
0.1
µF
0.1
µF
1 µF
+
+
Figure 7. CS5101A/CS5102A System Connection Diagram
calibration cycle on the CS5102A takes
2,882,040 master clock cycles to complete (ap-
proximately 1.8 seconds with a 1.6 MHz master
clock). The CS5101A’s and CS5102A’s STBY
output remains low throughout the calibration se-
quence, and a rising transition indicates the
device is ready for normal operation. While cali-
brating, the CS5101A and CS5102A will ignore
changes on the HOLD input.
be less than or equal to 10 kΩ. The system power
supplies, voltage reference, and clock should all
be established prior RST rising.
Single-Channel Operation
The CS5101A and CS5102A can alternatively be
used to sample one channel by tying the CH1/2
input high or low. The unused AIN pin should be
tied to the analog input signal or to AGND. (If
operating in free run mode, AIN1 and AIN2 must
To perform the reset function, a simple power-on
reset circuit can be built using a resistor and ca-
pacitor as shown in Figure 8. The resistor should
DS45F2
19
CIRRUS [ CIRRUS LOGIC ]
