CS49300 Family DSP
1.7. Switching Characteristics — Intel® Host Mode
(TA = 25 °C; VA, VD[3:1] = 2.5 V 5%; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 20 pF)
Parameter
Symbol
Min
Max
Unit
Tias
5
-
ns
Address setup before CS and RD low or CS and WR low
Address hold time after CS and RD low or CS and WR low
Delay between RD then CS low or CS then RD low
Tiah
Ticdr
Tidd
5
-
∞
21
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
-
Data valid after CS and RD low
(Note 3)
(Note 1)
Tirpw
Tidhr
Tidis
DCLKP + 10
CS and RD low for read
5
-
Data hold time after CS or RD high
Data high-Z after CS or RD high
-
22
-
(Note 2)
(Note 1)
(Note 1)
Tird
2*DCLKP + 10
2*DCLKP + 10
0
CS or RD high to CS and RD low for next read
CS or RD high to CS and WR low for next write
Delay between WR then CS low or CS then WR low
Data setup before CS or WR high
Tirdtw
Ticdw
Tidsu
Tiwpw
Tidhw
Tiwtrd
Tiwd
-
∞
-
20
DCLKP + 10
5
-
CS and WR low for write
(Note 1)
-
Data hold after CS or WR high
2*DCLKP + 10
2*DCLKP + 10
-
CS or WR high to CS and RD low for next read
CS or WR high to CS and WR low for next write
(Note 1)
(Note 1)
-
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =
1/DCLK. The DSP clock can be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns
DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for
characterization to minimize the effects of external bus capacitance.
3. See Tidd from Intel Host Mode in Table 6 on page 43
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DS339PP4
CIRRUS [ CIRRUS LOGIC ]
