CS49300 Family DSP
counter is used by certain application code for
audio/video synchronization purposes.
10.4. Byte Wide Digital Audio Data Input
Two types of byte wide parallel delivery are
supported by the CS493XX. If using one of the
parallel control modes described in Section 6.2,
“Parallel Host Communication” on page 41, then
the parallel interface can also be used for delivering
data. If using I2C or SPI control, then parallel
delivery can still be used using CMPCLK and
GPIO[7:0].
10.3. Compressed Data Input Port
The compressed data input port, or CDI, can be
used for both compressed and PCM data input.
Table 14 shows the mnemonic, pin name and pin
number of the pins associated with the CDI port on
the CS493XX.
Pin Name
SDATAN2
CMPDATA
SCLKN2
CMPCLK
LRCLKN2
CMPREQ
Pin Description
Serial Data In
Compressed Data In
Pin Number
10.4.1.Parallel Delivery with Parallel Control
27
If using the Intel or Motorola Parallel host interface
mode, the system designer can also choose to
deliver data through the byte wide parallel port.
The delivery mechanism is identical to that
discussed in Section 6.2, “Parallel Host
Communication” on page 41.
Serial Bit Clock
28
29
Frame Clock
Data Request Out
Table 14. Compressed Data Input Port
The compressed data input register (CMPDAT)
receives bytes of data when the host interface
writes to address 11b (A1 and A0 are both high).
The host should check level of the Compressed
Data FIFO before sending data. The CS493XX has
two means of indicating the Compressed Data
FIFO level. The MFB bit in the Host Control
Register is one indicator of the Compressed Data
FIFO level. The MFB bit remains low until the
FIFO threshold has been reached. The alternative is
to use the CMPREQ pin of the CS493XX. The
CMPREQ pin also remains low until the FIFO
threshold has been reached. The host has the option
of using either CMPREQ or the MFB bit.
The CDI is fully configurable including support for
I2S, left justified and multichannel formats. The
CDI can also be programmed for slave clocks,
where LRCLKN2 and SCLKN2 are inputs, or
master clocks, where LRCLKN2 and SCLKN2 are
outputs. In order for clocks to be mastered, the
internal PLL must be used.
In addition the CDI can be configured for bursty
compressed data input. Bursty audio delivery is a
special format in which only clock (CMPCLK) and
data (CMPDAT) are used to deliver compressed
data to the CS493XX (i.e. no frame clock or
LRCLK). A third line, CMPREQ, is used to request
more data from the host. It is an indicator that the
CS493XX internal FIFO is low on data and can
accept another burst. Typically this mode is used
for compressed data delivery where asynchronous
data transfer occurs in the system, i.e. in a system
such as a set-top box or HDTV. PCM data can not
be presented in this mode since data is interpreted
as a continuous stream with no word boundaries.
Data should be delivered to the CS493XX in blocks
of data. Before each block is delivered, the host
should check the MFB bit (or the CMPREQ pin). If
the MFB bit (CMPREQ) is low, then the host can
deliver a block of data one byte at a time. If the
MFB bit (CMPREQ) is high, no more data should
be sent to the CS493XX. Once the MFB bit
(CMPREQ) has gone low again, the host may send
another block of compressed audio data.
DS339PP4
69
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