CS49300 Family DSP
“Serial Communication” on page 33 discusses the
procedure required for placing the CS493XX into a
serial communication mode in more detail. For a
more thorough description of ABOOT’s behavior
after the rising edge of RESET please refer to
Section 8.2.1, “Autoboot INTREQ Behavior” on
page 57
8.2. Autoboot
Autoboot is a feature available on all DSPs in the
CS493XX family which gives the decoder the
ability to load application code into itself from an
external memory. Because external memory is
accessed through the external memory interface,
autoboot restricts the host control modes to serial
2
communication (I C or SPI). For this section the
The EMOE pin of the CS493XX is used for two
external memory interface shown in Figure 30, purposes. It generates clock pulses for the latches,
"External Memory Interface" on page 51 can be
referenced.
and it is used in conjunction with EXTMEM to
enable the outputs of the ROM. The first three
rising edges of EMOE are used to latch address
bytes, as shown in the diagram. The fourth low
pulse of EMOE is used to enable the ROM outputs.
When both EXTMEM and EMOE go low, the
EMAD[7:0] pins of the DSP become inputs and
await the data coming from the ROM.
RESET and ABOOT are the control pins which are
used to initiate an autoboot operation by the host
controller. It is important to be aware that the
ABOOT pin also serves as the INTREQ pin, which
means that it will be driven by the CS493XX when
not in reset. Due to this constraint, ABOOT should
be connected to an open-drain output of the
When comparing the memory system in Figure 30,
microcontroller so as to allow the specified pull-up "External Memory Interface" on page 51 to the
resistor to generate a logic high level. At the timing diagram of Figure 35, "Autoboot Timing
completion of a successful download, INTREQ Diagram" on page 56 there may appear to be a
(ABOOT) becomes an output and the host should
no longer drive it.
discrepancy. The timing diagram shows three
address cycles, but there are only two latches in the
illustration of the memory architecture. This
difference is a result of code size limitations. The
application code is guaranteed to fit into a 32
Kilobyte space, which means that only 15 address
bits will actually be used for retrieving code from
the ROM. Thus, the two latches catch the least
significant bytes, and the most significant byte is
dropped.
The timing for an autoboot sequence is illustrated
in Figure 35. The sequence is initiated by driving
RESET low and placing the decoder into reset. At
the rising edge of RESET, the ABOOT, WR, and
RD pins are sampled. If ABOOT is low when
sampled, and the WR and RD pins are set to
configure the device for serial communications, the
device will begin to autoboot (PSEL is a don’t care
for serial communications modes). Section 6.1,
RESET
ABOOT
EXTMEM
EMOE
EMW R
EMAD7:0
MA23:16
MA15:8
MA7:0
Data7:0
Figure 35. Autoboot Timing Diagram
56
DS339PP4
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