CS49300 Family DSP
4.3 Ground ...................................................................................................................... 32
4.4 Pads ......................................................................................................................... 32
5. CLOCKING ..................................................................................................................... 32
6. CONTROL ...................................................................................................................... 32
6.1 Serial Communication .............................................................................................. 33
6.1.1 SPI Communication ...................................................................................... 33
6.1.2 I2C Communication ...................................................................................... 35
6.1.3 INTREQ Behavior: A Special Case .............................................................. 39
6.2 Parallel Host Communication ................................................................................... 41
6.2.1 Intel Parallel Host Communication Mode ..................................................... 43
6.2.2 Motorola Parallel Host Communication Mode .............................................. 45
6.2.3 Procedures for Parallel Host Mode Communication .................................... 46
7. EXTERNAL MEMORY .................................................................................................... 48
7.1 Non-Paged Memory ................................................................................................. 49
7.2 Paged Memory ........................................................................................................ 49
8. BOOT PROCEDURE & RESET ..................................................................................... 52
8.1 Host Boot .................................................................................................................. 52
8.1.1 Serial Download Sequence .......................................................................... 52
8.1.2 Parallel Download Sequence ....................................................................... 55
8.2 Autoboot ................................................................................................................... 56
8.2.1 Autoboot INTREQ Behavior ......................................................................... 57
8.3 Decreasing Autoboot Times Using GFABT Codes (Fast Autoboot) ......................... 59
8.3.1 Design Considerations when using GFABT Codes ...................................... 61
8.4 Internal Boot ............................................................................................................. 61
8.5 Application Failure Boot Message ............................................................................ 61
8.6 Resetting the CS493XX ............................................................................................ 61
8.7 External Memory Examples ...................................................................................... 63
8.7.1 Non-Paged Autoboot Memory ...................................................................... 63
8.7.2 32 Kilobyte Paged Autoboot Memory ........................................................... 64
8.8 CDB49300-MEMA.0 ................................................................................................. 65
9. HARDWARE CONFIGURATION ................................................................................... 67
10.DIGITAL INPUT & OUTPUT ........................................................................................... 67
10.1 Digital Audio Formats .............................................................................................. 67
10.1.1 I2S .............................................................................................................. 67
10.1.2 Left Justified ............................................................................................... 67
10.1.3 Multichannel ............................................................................................... 67
10.2 Digital Audio Input Port ........................................................................................... 68
10.3 Compressed Data Input Port ................................................................................... 69
10.4 Byte Wide Digital Audio Data Input ......................................................................... 69
10.4.1 Parallel Delivery with Parallel Control ........................................................ 69
10.4.2 Parallel Delivery with Serial Control ........................................................... 70
10.5 Digital Audio Output Port ......................................................................................... 70
10.5.1 IEC60958 Output ........................................................................................ 71
11.HARDWARE CONFIGURATION ................................................................................... 72
11.1 Address Checking ................................................................................................... 72
11.2 Input Data Hardware Configuration ........................................................................ 72
11.2.1 Input Configuration Considerations ......................................................... 75
11.3 Output Data Hardware Configuration ...................................................................... 76
11.3.1 Output Configuration Considerations ........................................................ 78
11.4 Creating Hardware Configuration Messages .......................................................... 78
DS339PP4
3
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