CS4397
5.0 PIN DESCRIPTION - DSD MODE
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode M2(SCL/CCLK)
Refer to PCM mode M0(SDA/CDOUT)
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Master Clock
DSD Serial Clock
Master Clock Mode
Left Channel Data
Right Channel Data
RST
M4(ADO/CS)
M3(AD1/CDIN)
VREF
FILT+
FILT-
Refer to PCM mode
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
Refer to PCM mode
CMOUT
AOUTL-
AOUTL+
VA
AGND
AOUTR+
AOUTR-
AGND
MUTEC
C/H
DGND
VD
VD
DGND
9
MCLK
10
11
12
13
14
DSD_SCLK
CLKMODE
DSD_L
DSD_R
MUTE
Master Clock - MCLK
Pin 10, Input
Function:
The master clock frequency must be either 4x or 6x the DSD data rate for 64x oversampled DSD data
and 2x or 3x the DSD data rate for 128x oversampled DSD data, refer to Table 7.
CLKMODE
Pin 12, Input
Function:
This pin determines the allowable Master Clock to DSD data ratio as defined in Table 7.
CLKMODE
0
1
64x
4x
6x
DSD Over-
Sampling Ratio
128x
2x
3x
Table 7. MCLK to DSD Data Rate Clock Ratios
DSD Serial Clock - DSD_SCLK
Pin 11, Input
Function:
Clocks the individual bits of the DSD audio data into the DSD_L and DSD_R pins.
Audio Data - DSD_L and DSD_R
Pins 13 and 14, Inputs
Function:
Direct Stream Digital audio data is clocked into DSD_L and DSD_R via the DSD serial clock.
DS333F1
23
CIRRUS [ CIRRUS LOGIC ]
