CS4397
3.0 REGISTER DESCRIPTION
3.1 DIFFERENTIAL DC OFFSET CALIBRATION
Mode Control Register (address 01h)
7
6
5
4
3
2
1
0
CAL
MUTE
M4
M3
M2
M1
M0
PDN
Access:
2
R/W in I C and SPI.
Default:
0 - Disabled
Function:
Enabling this function will initiate a calibration to minimize the differential DC offset. This function will be
automatically reset following completion of the calibration sequence.
CAL
MODE
0
1
Disabled : CAL complete
Enabled : CAL initiated
Table 1.
3.2 SOFT MUTE
Mode Control Register (address 01h)
7
6
5
4
3
2
1
0
CAL
M4
M3
M2
M1
M0
PDN
MUTE
Access:
2
R/W in I C and SPI.
Default:
0 - Enabled
Function:
The analog outputs will ramp to a muted state when enabled. The ramp requires 1152 left/right clock cy-
cles in Single Speed, 2304 cycles in Double Speed and 4608 cycles in Quad Speed mode. The bias volt-
age on the outputs will be retained and MUTEC will go low at the completion of the ramp period.
The analog outputs will ramp to a normal state when this function transitions from the enabled to disabled
state. The ramp requires 1152 left/right clock cycles in Single Speed, 2304 cycles in Double Speed and
4608 cycles in Quad Speed mode. The MUTEC will go high immediately on disabling of MUTE.
MODE
MUTE
0
1
Enabled
Disabled
Table 2.
16
DS333F1
CIRRUS [ CIRRUS LOGIC ]
